--- /dev/null
+(edif test (edifVersion 2 0 0) (edifLevel 0) (keywordMap (keywordLevel 0))
+(status (written (timeStamp 2006 2 18 19 6 6)
+ (author "Xilinx, Inc.")
+ (program "Xilinx CORE Generator" (version "Xilinx CORE Generator 7.1.04i; Cores Update # 3"))))
+ (comment "
+ This file is owned and controlled by Xilinx and must be used
+ solely for design, simulation, implementation and creation of
+ design files limited to Xilinx devices or technologies. Use
+ with non-Xilinx devices or technologies is expressly prohibited
+ and immediately terminates your license.
+
+ XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION 'AS IS'
+ SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR
+ XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION
+ AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION
+ OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS
+ IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
+ AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
+ FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY
+ WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
+ IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
+ REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
+ INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ FOR A PARTICULAR PURPOSE.
+
+ Xilinx products are not intended for use in life support
+ appliances, devices, or systems. Use in such applications are
+ expressly prohibited.
+
+ (c) Copyright 1995-2005 Xilinx, Inc.
+ All rights reserved.
+
+ ")
+ (comment "Core parameters: ")
+ (comment "c_reg_inputsb = 0 ")
+ (comment "c_reg_inputsa = 0 ")
+ (comment "c_has_ndb = 0 ")
+ (comment "c_has_nda = 0 ")
+ (comment "c_ytop_addr = 1024 ")
+ (comment "c_has_rfdb = 0 ")
+ (comment "c_has_rfda = 0 ")
+ (comment "c_ywea_is_high = 1 ")
+ (comment "c_yena_is_high = 1 ")
+ (comment "InstanceName = async_fifo_8_8_128_fifo_generator_v2_2_xst_1_blkmemdp_v6_2_xst ")
+ (comment "c_yhierarchy = hierarchy1 ")
+ (comment "c_yclka_is_rising = 1 ")
+ (comment "c_family = virtex2p ")
+ (comment "c_ysinita_is_high = 1 ")
+ (comment "c_ybottom_addr = 0 ")
+ (comment "c_width_b = 8 ")
+ (comment "c_width_a = 8 ")
+ (comment "c_sinita_value = 0000 ")
+ (comment "c_sinitb_value = 00 ")
+ (comment "c_limit_data_pitch = 18 ")
+ (comment "c_write_modeb = 0 ")
+ (comment "c_write_modea = 0 ")
+ (comment "c_has_rdyb = 0 ")
+ (comment "c_yuse_single_primitive = 0 ")
+ (comment "c_has_rdya = 0 ")
+ (comment "c_addra_width = 7 ")
+ (comment "c_addrb_width = 7 ")
+ (comment "c_has_limit_data_pitch = 0 ")
+ (comment "c_default_data = 0000 ")
+ (comment "c_pipe_stages_b = 0 ")
+ (comment "c_yweb_is_high = 1 ")
+ (comment "c_yenb_is_high = 1 ")
+ (comment "c_pipe_stages_a = 0 ")
+ (comment "c_yclkb_is_rising = 1 ")
+ (comment "c_yydisable_warnings = 1 ")
+ (comment "c_enable_rlocs = 0 ")
+ (comment "c_ysinitb_is_high = 1 ")
+ (comment "c_has_web = 0 ")
+ (comment "c_has_default_data = 1 ")
+ (comment "c_has_wea = 1 ")
+ (comment "c_has_sinitb = 1 ")
+ (comment "c_has_sinita = 1 ")
+ (comment "c_has_dinb = 0 ")
+ (comment "c_has_dina = 1 ")
+ (comment "c_ymake_bmm = 0 ")
+ (comment "c_has_enb = 1 ")
+ (comment "c_has_ena = 0 ")
+ (comment "c_mem_init_file = mif_file_16_1 ")
+ (comment "c_depth_b = 128 ")
+ (comment "c_depth_a = 128 ")
+ (comment "c_has_doutb = 1 ")
+ (comment "c_has_douta = 0 ")
+ (comment "c_yprimitive_type = 4kx4 ")
+ (external xilinxun (edifLevel 0)
+ (technology (numberDefinition))
+ (cell VCC (cellType GENERIC)
+ (view view_1 (viewType NETLIST)
+ (interface
+ (port P (direction OUTPUT))
+ )
+ )
+ )
+ (cell GND (cellType GENERIC)
+ (view view_1 (viewType NETLIST)
+ (interface
+ (port G (direction OUTPUT))
+ )
+ )
+ )
+ (cell RAMB16_S9_S9 (cellType GENERIC)
+ (view view_1 (viewType NETLIST)
+ (interface
+ (port WEA (direction INPUT))
+ (port ENA (direction INPUT))
+ (port SSRA (direction INPUT))
+ (port CLKA (direction INPUT))
+ (port (rename DIA_0_ "DIA<0>") (direction INPUT))
+ (port (rename DIA_1_ "DIA<1>") (direction INPUT))
+ (port (rename DIA_2_ "DIA<2>") (direction INPUT))
+ (port (rename DIA_3_ "DIA<3>") (direction INPUT))
+ (port (rename DIA_4_ "DIA<4>") (direction INPUT))
+ (port (rename DIA_5_ "DIA<5>") (direction INPUT))
+ (port (rename DIA_6_ "DIA<6>") (direction INPUT))
+ (port (rename DIA_7_ "DIA<7>") (direction INPUT))
+ (port (rename DOA_0_ "DOA<0>") (direction OUTPUT))
+ (port (rename DOA_1_ "DOA<1>") (direction OUTPUT))
+ (port (rename DOA_2_ "DOA<2>") (direction OUTPUT))
+ (port (rename DOA_3_ "DOA<3>") (direction OUTPUT))
+ (port (rename DOA_4_ "DOA<4>") (direction OUTPUT))
+ (port (rename DOA_5_ "DOA<5>") (direction OUTPUT))
+ (port (rename DOA_6_ "DOA<6>") (direction OUTPUT))
+ (port (rename DOA_7_ "DOA<7>") (direction OUTPUT))
+ (port (rename ADDRA_0_ "ADDRA<0>") (direction INPUT))
+ (port (rename ADDRA_1_ "ADDRA<1>") (direction INPUT))
+ (port (rename ADDRA_2_ "ADDRA<2>") (direction INPUT))
+ (port (rename ADDRA_3_ "ADDRA<3>") (direction INPUT))
+ (port (rename ADDRA_4_ "ADDRA<4>") (direction INPUT))
+ (port (rename ADDRA_5_ "ADDRA<5>") (direction INPUT))
+ (port (rename ADDRA_6_ "ADDRA<6>") (direction INPUT))
+ (port (rename ADDRA_7_ "ADDRA<7>") (direction INPUT))
+ (port (rename ADDRA_8_ "ADDRA<8>") (direction INPUT))
+ (port (rename ADDRA_9_ "ADDRA<9>") (direction INPUT))
+ (port (rename ADDRA_10_ "ADDRA<10>") (direction INPUT))
+ (port (rename DIPA_0_ "DIPA<0>") (direction INPUT))
+ (port (rename DOPA_0_ "DOPA<0>") (direction OUTPUT))
+ (port WEB (direction INPUT))
+ (port ENB (direction INPUT))
+ (port SSRB (direction INPUT))
+ (port CLKB (direction INPUT))
+ (port (rename DIB_0_ "DIB<0>") (direction INPUT))
+ (port (rename DIB_1_ "DIB<1>") (direction INPUT))
+ (port (rename DIB_2_ "DIB<2>") (direction INPUT))
+ (port (rename DIB_3_ "DIB<3>") (direction INPUT))
+ (port (rename DIB_4_ "DIB<4>") (direction INPUT))
+ (port (rename DIB_5_ "DIB<5>") (direction INPUT))
+ (port (rename DIB_6_ "DIB<6>") (direction INPUT))
+ (port (rename DIB_7_ "DIB<7>") (direction INPUT))
+ (port (rename DOB_0_ "DOB<0>") (direction OUTPUT))
+ (port (rename DOB_1_ "DOB<1>") (direction OUTPUT))
+ (port (rename DOB_2_ "DOB<2>") (direction OUTPUT))
+ (port (rename DOB_3_ "DOB<3>") (direction OUTPUT))
+ (port (rename DOB_4_ "DOB<4>") (direction OUTPUT))
+ (port (rename DOB_5_ "DOB<5>") (direction OUTPUT))
+ (port (rename DOB_6_ "DOB<6>") (direction OUTPUT))
+ (port (rename DOB_7_ "DOB<7>") (direction OUTPUT))
+ (port (rename ADDRB_0_ "ADDRB<0>") (direction INPUT))
+ (port (rename ADDRB_1_ "ADDRB<1>") (direction INPUT))
+ (port (rename ADDRB_2_ "ADDRB<2>") (direction INPUT))
+ (port (rename ADDRB_3_ "ADDRB<3>") (direction INPUT))
+ (port (rename ADDRB_4_ "ADDRB<4>") (direction INPUT))
+ (port (rename ADDRB_5_ "ADDRB<5>") (direction INPUT))
+ (port (rename ADDRB_6_ "ADDRB<6>") (direction INPUT))
+ (port (rename ADDRB_7_ "ADDRB<7>") (direction INPUT))
+ (port (rename ADDRB_8_ "ADDRB<8>") (direction INPUT))
+ (port (rename ADDRB_9_ "ADDRB<9>") (direction INPUT))
+ (port (rename ADDRB_10_ "ADDRB<10>") (direction INPUT))
+ (port (rename DIPB_0_ "DIPB<0>") (direction INPUT))
+ (port (rename DOPB_0_ "DOPB<0>") (direction OUTPUT))
+ )
+ )
+ )
+ )
+(library test_lib (edifLevel 0) (technology (numberDefinition (scale 1 (E 1 -12) (unit Time))))
+(cell async_fifo_8_8_128_fifo_generator_v2_2_xst_1_blkmemdp_v6_2_xst
+ (cellType GENERIC) (view view_1 (viewType NETLIST)
+ (interface
+ (port ( rename dina_7_ "dina<7>") (direction INPUT))
+ (port ( rename dina_6_ "dina<6>") (direction INPUT))
+ (port ( rename dina_5_ "dina<5>") (direction INPUT))
+ (port ( rename dina_4_ "dina<4>") (direction INPUT))
+ (port ( rename dina_3_ "dina<3>") (direction INPUT))
+ (port ( rename dina_2_ "dina<2>") (direction INPUT))
+ (port ( rename dina_1_ "dina<1>") (direction INPUT))
+ (port ( rename dina_0_ "dina<0>") (direction INPUT))
+ (port ( rename dinb_7_ "dinb<7>") (direction INPUT))
+ (port ( rename dinb_6_ "dinb<6>") (direction INPUT))
+ (port ( rename dinb_5_ "dinb<5>") (direction INPUT))
+ (port ( rename dinb_4_ "dinb<4>") (direction INPUT))
+ (port ( rename dinb_3_ "dinb<3>") (direction INPUT))
+ (port ( rename dinb_2_ "dinb<2>") (direction INPUT))
+ (port ( rename dinb_1_ "dinb<1>") (direction INPUT))
+ (port ( rename dinb_0_ "dinb<0>") (direction INPUT))
+ (port ( rename ena "ena") (direction INPUT))
+ (port ( rename enb "enb") (direction INPUT))
+ (port ( rename wea "wea") (direction INPUT))
+ (port ( rename web "web") (direction INPUT))
+ (port ( rename sinita "sinita") (direction INPUT))
+ (port ( rename sinitb "sinitb") (direction INPUT))
+ (port ( rename nda "nda") (direction INPUT))
+ (port ( rename ndb "ndb") (direction INPUT))
+ (port ( rename clka "clka") (direction INPUT))
+ (port ( rename clkb "clkb") (direction INPUT))
+ (port ( rename addra_6_ "addra<6>") (direction INPUT))
+ (port ( rename addra_5_ "addra<5>") (direction INPUT))
+ (port ( rename addra_4_ "addra<4>") (direction INPUT))
+ (port ( rename addra_3_ "addra<3>") (direction INPUT))
+ (port ( rename addra_2_ "addra<2>") (direction INPUT))
+ (port ( rename addra_1_ "addra<1>") (direction INPUT))
+ (port ( rename addra_0_ "addra<0>") (direction INPUT))
+ (port ( rename addrb_6_ "addrb<6>") (direction INPUT))
+ (port ( rename addrb_5_ "addrb<5>") (direction INPUT))
+ (port ( rename addrb_4_ "addrb<4>") (direction INPUT))
+ (port ( rename addrb_3_ "addrb<3>") (direction INPUT))
+ (port ( rename addrb_2_ "addrb<2>") (direction INPUT))
+ (port ( rename addrb_1_ "addrb<1>") (direction INPUT))
+ (port ( rename addrb_0_ "addrb<0>") (direction INPUT))
+ (port ( rename rdya "rdya") (direction OUTPUT))
+ (port ( rename rdyb "rdyb") (direction OUTPUT))
+ (port ( rename rfda "rfda") (direction OUTPUT))
+ (port ( rename rfdb "rfdb") (direction OUTPUT))
+ (port ( rename douta_7_ "douta<7>") (direction OUTPUT))
+ (port ( rename douta_6_ "douta<6>") (direction OUTPUT))
+ (port ( rename douta_5_ "douta<5>") (direction OUTPUT))
+ (port ( rename douta_4_ "douta<4>") (direction OUTPUT))
+ (port ( rename douta_3_ "douta<3>") (direction OUTPUT))
+ (port ( rename douta_2_ "douta<2>") (direction OUTPUT))
+ (port ( rename douta_1_ "douta<1>") (direction OUTPUT))
+ (port ( rename douta_0_ "douta<0>") (direction OUTPUT))
+ (port ( rename doutb_7_ "doutb<7>") (direction OUTPUT))
+ (port ( rename doutb_6_ "doutb<6>") (direction OUTPUT))
+ (port ( rename doutb_5_ "doutb<5>") (direction OUTPUT))
+ (port ( rename doutb_4_ "doutb<4>") (direction OUTPUT))
+ (port ( rename doutb_3_ "doutb<3>") (direction OUTPUT))
+ (port ( rename doutb_2_ "doutb<2>") (direction OUTPUT))
+ (port ( rename doutb_1_ "doutb<1>") (direction OUTPUT))
+ (port ( rename doutb_0_ "doutb<0>") (direction OUTPUT))
+ )
+ (contents
+ (instance VCC (viewRef view_1 (cellRef VCC (libraryRef xilinxun))))
+ (instance GND (viewRef view_1 (cellRef GND (libraryRef xilinxun))))
+ (instance (rename async_fifo_8_8_128_fifo_generator_v2_2_xst_1_blkmemdp_v6_2_xst_bm_mem_arch_v2_prim_3_b1_chk0_col_0_b2_mextd_arch_v2_c1_ram1_v2_d2048_by9_newSim8 "async_fifo_8_8_128_fifo_generator_v2_2_xst_1_blkmemdp_v6_2_xst/bm/mem/arch_v2/prim/3/b1/chk0/col/0/b2/mextd/arch_v2/c1/ram1/v2/d2048/by9/newSim8")
+ (viewRef view_1 (cellRef RAMB16_S9_S9 (libraryRef xilinxun)))
+ (property INIT_00 (string "0000000000000000000000000000000000000000000000000000000000000000"))
+ (property INIT_01 (string "0000000000000000000000000000000000000000000000000000000000000000"))
+ (property INIT_02 (string "0000000000000000000000000000000000000000000000000000000000000000"))
+ (property INIT_03 (string "0000000000000000000000000000000000000000000000000000000000000000"))
+ (property INIT_04 (string "0000000000000000000000000000000000000000000000000000000000000000"))
+ (property INIT_05 (string "0000000000000000000000000000000000000000000000000000000000000000"))
+ (property INIT_06 (string "0000000000000000000000000000000000000000000000000000000000000000"))
+ (property INIT_07 (string "0000000000000000000000000000000000000000000000000000000000000000"))
+ (property INIT_08 (string "0000000000000000000000000000000000000000000000000000000000000000"))
+ (property INIT_09 (string "0000000000000000000000000000000000000000000000000000000000000000"))
+ (property INIT_0A (string "0000000000000000000000000000000000000000000000000000000000000000"))
+ (property INIT_0B (string "0000000000000000000000000000000000000000000000000000000000000000"))
+ (property INIT_0C (string "0000000000000000000000000000000000000000000000000000000000000000"))
+ (property INIT_0D (string "0000000000000000000000000000000000000000000000000000000000000000"))
+ (property INIT_0E (string "0000000000000000000000000000000000000000000000000000000000000000"))
+ (property INIT_0F (string "0000000000000000000000000000000000000000000000000000000000000000"))
+ (property INIT_10 (string "0000000000000000000000000000000000000000000000000000000000000000"))
+ (property INIT_11 (string "0000000000000000000000000000000000000000000000000000000000000000"))
+ (property INIT_12 (string "0000000000000000000000000000000000000000000000000000000000000000"))
+ (property INIT_13 (string "0000000000000000000000000000000000000000000000000000000000000000"))
+ (property INIT_14 (string "0000000000000000000000000000000000000000000000000000000000000000"))
+ (property INIT_15 (string "0000000000000000000000000000000000000000000000000000000000000000"))
+ (property INIT_16 (string "0000000000000000000000000000000000000000000000000000000000000000"))
+ (property INIT_17 (string "0000000000000000000000000000000000000000000000000000000000000000"))
+ (property INIT_18 (string "0000000000000000000000000000000000000000000000000000000000000000"))
+ (property INIT_19 (string "0000000000000000000000000000000000000000000000000000000000000000"))
+ (property INIT_1A (string "0000000000000000000000000000000000000000000000000000000000000000"))
+ (property INIT_1B (string "0000000000000000000000000000000000000000000000000000000000000000"))
+ (property INIT_1C (string "0000000000000000000000000000000000000000000000000000000000000000"))
+ (property INIT_1D (string "0000000000000000000000000000000000000000000000000000000000000000"))
+ (property INIT_1E (string "0000000000000000000000000000000000000000000000000000000000000000"))
+ (property INIT_1F (string "0000000000000000000000000000000000000000000000000000000000000000"))
+ (property INIT_20 (string "0000000000000000000000000000000000000000000000000000000000000000"))
+ (property INIT_21 (string "0000000000000000000000000000000000000000000000000000000000000000"))
+ (property INIT_22 (string "0000000000000000000000000000000000000000000000000000000000000000"))
+ (property INIT_23 (string "0000000000000000000000000000000000000000000000000000000000000000"))
+ (property INIT_24 (string "0000000000000000000000000000000000000000000000000000000000000000"))
+ (property INIT_25 (string "0000000000000000000000000000000000000000000000000000000000000000"))
+ (property INIT_26 (string "0000000000000000000000000000000000000000000000000000000000000000"))
+ (property INIT_27 (string "0000000000000000000000000000000000000000000000000000000000000000"))
+ (property INIT_28 (string "0000000000000000000000000000000000000000000000000000000000000000"))
+ (property INIT_29 (string "0000000000000000000000000000000000000000000000000000000000000000"))
+ (property INIT_2A (string "0000000000000000000000000000000000000000000000000000000000000000"))
+ (property INIT_2B (string "0000000000000000000000000000000000000000000000000000000000000000"))
+ (property INIT_2C (string "0000000000000000000000000000000000000000000000000000000000000000"))
+ (property INIT_2D (string "0000000000000000000000000000000000000000000000000000000000000000"))
+ (property INIT_2E (string "0000000000000000000000000000000000000000000000000000000000000000"))
+ (property INIT_2F (string "0000000000000000000000000000000000000000000000000000000000000000"))
+ (property INIT_30 (string "0000000000000000000000000000000000000000000000000000000000000000"))
+ (property INIT_31 (string "0000000000000000000000000000000000000000000000000000000000000000"))
+ (property INIT_32 (string "0000000000000000000000000000000000000000000000000000000000000000"))
+ (property INIT_33 (string "0000000000000000000000000000000000000000000000000000000000000000"))
+ (property INIT_34 (string "0000000000000000000000000000000000000000000000000000000000000000"))
+ (property INIT_35 (string "0000000000000000000000000000000000000000000000000000000000000000"))
+ (property INIT_36 (string "0000000000000000000000000000000000000000000000000000000000000000"))
+ (property INIT_37 (string "0000000000000000000000000000000000000000000000000000000000000000"))
+ (property INIT_38 (string "0000000000000000000000000000000000000000000000000000000000000000"))
+ (property INIT_39 (string "0000000000000000000000000000000000000000000000000000000000000000"))
+ (property INIT_3A (string "0000000000000000000000000000000000000000000000000000000000000000"))
+ (property INIT_3B (string "0000000000000000000000000000000000000000000000000000000000000000"))
+ (property INIT_3C (string "0000000000000000000000000000000000000000000000000000000000000000"))
+ (property INIT_3D (string "0000000000000000000000000000000000000000000000000000000000000000"))
+ (property INIT_3E (string "0000000000000000000000000000000000000000000000000000000000000000"))
+ (property INIT_3F (string "0000000000000000000000000000000000000000000000000000000000000000"))
+ (property INITP_00 (string "0000000000000000000000000000000000000000000000000000000000000000"))
+ (property INITP_01 (string "0000000000000000000000000000000000000000000000000000000000000000"))
+ (property INITP_02 (string "0000000000000000000000000000000000000000000000000000000000000000"))
+ (property INITP_03 (string "0000000000000000000000000000000000000000000000000000000000000000"))
+ (property INITP_04 (string "0000000000000000000000000000000000000000000000000000000000000000"))
+ (property INITP_05 (string "0000000000000000000000000000000000000000000000000000000000000000"))
+ (property INITP_06 (string "0000000000000000000000000000000000000000000000000000000000000000"))
+ (property INITP_07 (string "0000000000000000000000000000000000000000000000000000000000000000"))
+ (property WRITE_MODE_A (string "WRITE_FIRST"))
+ (property INIT_A (string "000"))
+ (property SRVAL_A (string "000"))
+ (property WRITE_MODE_B (string "WRITE_FIRST"))
+ (property INIT_B (string "000"))
+ (property SRVAL_B (string "000"))
+ )
+ (net (rename N0 "Gnd")
+ (joined
+ (portRef G (instanceRef GND))
+ (portRef WEB (instanceRef async_fifo_8_8_128_fifo_generator_v2_2_xst_1_blkmemdp_v6_2_xst_bm_mem_arch_v2_prim_3_b1_chk0_col_0_b2_mextd_arch_v2_c1_ram1_v2_d2048_by9_newSim8))
+ (portRef ADDRA_7_ (instanceRef async_fifo_8_8_128_fifo_generator_v2_2_xst_1_blkmemdp_v6_2_xst_bm_mem_arch_v2_prim_3_b1_chk0_col_0_b2_mextd_arch_v2_c1_ram1_v2_d2048_by9_newSim8))
+ (portRef ADDRA_8_ (instanceRef async_fifo_8_8_128_fifo_generator_v2_2_xst_1_blkmemdp_v6_2_xst_bm_mem_arch_v2_prim_3_b1_chk0_col_0_b2_mextd_arch_v2_c1_ram1_v2_d2048_by9_newSim8))
+ (portRef ADDRA_9_ (instanceRef async_fifo_8_8_128_fifo_generator_v2_2_xst_1_blkmemdp_v6_2_xst_bm_mem_arch_v2_prim_3_b1_chk0_col_0_b2_mextd_arch_v2_c1_ram1_v2_d2048_by9_newSim8))
+ (portRef ADDRA_10_ (instanceRef async_fifo_8_8_128_fifo_generator_v2_2_xst_1_blkmemdp_v6_2_xst_bm_mem_arch_v2_prim_3_b1_chk0_col_0_b2_mextd_arch_v2_c1_ram1_v2_d2048_by9_newSim8))
+ (portRef DIPA_0_ (instanceRef async_fifo_8_8_128_fifo_generator_v2_2_xst_1_blkmemdp_v6_2_xst_bm_mem_arch_v2_prim_3_b1_chk0_col_0_b2_mextd_arch_v2_c1_ram1_v2_d2048_by9_newSim8))
+ (portRef ADDRB_7_ (instanceRef async_fifo_8_8_128_fifo_generator_v2_2_xst_1_blkmemdp_v6_2_xst_bm_mem_arch_v2_prim_3_b1_chk0_col_0_b2_mextd_arch_v2_c1_ram1_v2_d2048_by9_newSim8))
+ (portRef ADDRB_8_ (instanceRef async_fifo_8_8_128_fifo_generator_v2_2_xst_1_blkmemdp_v6_2_xst_bm_mem_arch_v2_prim_3_b1_chk0_col_0_b2_mextd_arch_v2_c1_ram1_v2_d2048_by9_newSim8))
+ (portRef ADDRB_9_ (instanceRef async_fifo_8_8_128_fifo_generator_v2_2_xst_1_blkmemdp_v6_2_xst_bm_mem_arch_v2_prim_3_b1_chk0_col_0_b2_mextd_arch_v2_c1_ram1_v2_d2048_by9_newSim8))
+ (portRef ADDRB_10_ (instanceRef async_fifo_8_8_128_fifo_generator_v2_2_xst_1_blkmemdp_v6_2_xst_bm_mem_arch_v2_prim_3_b1_chk0_col_0_b2_mextd_arch_v2_c1_ram1_v2_d2048_by9_newSim8))
+ (portRef DIB_0_ (instanceRef async_fifo_8_8_128_fifo_generator_v2_2_xst_1_blkmemdp_v6_2_xst_bm_mem_arch_v2_prim_3_b1_chk0_col_0_b2_mextd_arch_v2_c1_ram1_v2_d2048_by9_newSim8))
+ (portRef DIB_1_ (instanceRef async_fifo_8_8_128_fifo_generator_v2_2_xst_1_blkmemdp_v6_2_xst_bm_mem_arch_v2_prim_3_b1_chk0_col_0_b2_mextd_arch_v2_c1_ram1_v2_d2048_by9_newSim8))
+ (portRef DIB_2_ (instanceRef async_fifo_8_8_128_fifo_generator_v2_2_xst_1_blkmemdp_v6_2_xst_bm_mem_arch_v2_prim_3_b1_chk0_col_0_b2_mextd_arch_v2_c1_ram1_v2_d2048_by9_newSim8))
+ (portRef DIB_3_ (instanceRef async_fifo_8_8_128_fifo_generator_v2_2_xst_1_blkmemdp_v6_2_xst_bm_mem_arch_v2_prim_3_b1_chk0_col_0_b2_mextd_arch_v2_c1_ram1_v2_d2048_by9_newSim8))
+ (portRef DIB_4_ (instanceRef async_fifo_8_8_128_fifo_generator_v2_2_xst_1_blkmemdp_v6_2_xst_bm_mem_arch_v2_prim_3_b1_chk0_col_0_b2_mextd_arch_v2_c1_ram1_v2_d2048_by9_newSim8))
+ (portRef DIB_5_ (instanceRef async_fifo_8_8_128_fifo_generator_v2_2_xst_1_blkmemdp_v6_2_xst_bm_mem_arch_v2_prim_3_b1_chk0_col_0_b2_mextd_arch_v2_c1_ram1_v2_d2048_by9_newSim8))
+ (portRef DIB_6_ (instanceRef async_fifo_8_8_128_fifo_generator_v2_2_xst_1_blkmemdp_v6_2_xst_bm_mem_arch_v2_prim_3_b1_chk0_col_0_b2_mextd_arch_v2_c1_ram1_v2_d2048_by9_newSim8))
+ (portRef DIB_7_ (instanceRef async_fifo_8_8_128_fifo_generator_v2_2_xst_1_blkmemdp_v6_2_xst_bm_mem_arch_v2_prim_3_b1_chk0_col_0_b2_mextd_arch_v2_c1_ram1_v2_d2048_by9_newSim8))
+ (portRef DIPB_0_ (instanceRef async_fifo_8_8_128_fifo_generator_v2_2_xst_1_blkmemdp_v6_2_xst_bm_mem_arch_v2_prim_3_b1_chk0_col_0_b2_mextd_arch_v2_c1_ram1_v2_d2048_by9_newSim8))
+ )
+ )
+ (net (rename N1 "Vcc")
+ (joined
+ (portRef P (instanceRef VCC))
+ (portRef ENA (instanceRef async_fifo_8_8_128_fifo_generator_v2_2_xst_1_blkmemdp_v6_2_xst_bm_mem_arch_v2_prim_3_b1_chk0_col_0_b2_mextd_arch_v2_c1_ram1_v2_d2048_by9_newSim8))
+ )
+ )
+ (net (rename N2 "dina<7>")
+ (joined
+ (portRef dina_7_)
+ (portRef DIA_7_ (instanceRef async_fifo_8_8_128_fifo_generator_v2_2_xst_1_blkmemdp_v6_2_xst_bm_mem_arch_v2_prim_3_b1_chk0_col_0_b2_mextd_arch_v2_c1_ram1_v2_d2048_by9_newSim8))
+ )
+ )
+ (net (rename N3 "dina<6>")
+ (joined
+ (portRef dina_6_)
+ (portRef DIA_6_ (instanceRef async_fifo_8_8_128_fifo_generator_v2_2_xst_1_blkmemdp_v6_2_xst_bm_mem_arch_v2_prim_3_b1_chk0_col_0_b2_mextd_arch_v2_c1_ram1_v2_d2048_by9_newSim8))
+ )
+ )
+ (net (rename N4 "dina<5>")
+ (joined
+ (portRef dina_5_)
+ (portRef DIA_5_ (instanceRef async_fifo_8_8_128_fifo_generator_v2_2_xst_1_blkmemdp_v6_2_xst_bm_mem_arch_v2_prim_3_b1_chk0_col_0_b2_mextd_arch_v2_c1_ram1_v2_d2048_by9_newSim8))
+ )
+ )
+ (net (rename N5 "dina<4>")
+ (joined
+ (portRef dina_4_)
+ (portRef DIA_4_ (instanceRef async_fifo_8_8_128_fifo_generator_v2_2_xst_1_blkmemdp_v6_2_xst_bm_mem_arch_v2_prim_3_b1_chk0_col_0_b2_mextd_arch_v2_c1_ram1_v2_d2048_by9_newSim8))
+ )
+ )
+ (net (rename N6 "dina<3>")
+ (joined
+ (portRef dina_3_)
+ (portRef DIA_3_ (instanceRef async_fifo_8_8_128_fifo_generator_v2_2_xst_1_blkmemdp_v6_2_xst_bm_mem_arch_v2_prim_3_b1_chk0_col_0_b2_mextd_arch_v2_c1_ram1_v2_d2048_by9_newSim8))
+ )
+ )
+ (net (rename N7 "dina<2>")
+ (joined
+ (portRef dina_2_)
+ (portRef DIA_2_ (instanceRef async_fifo_8_8_128_fifo_generator_v2_2_xst_1_blkmemdp_v6_2_xst_bm_mem_arch_v2_prim_3_b1_chk0_col_0_b2_mextd_arch_v2_c1_ram1_v2_d2048_by9_newSim8))
+ )
+ )
+ (net (rename N8 "dina<1>")
+ (joined
+ (portRef dina_1_)
+ (portRef DIA_1_ (instanceRef async_fifo_8_8_128_fifo_generator_v2_2_xst_1_blkmemdp_v6_2_xst_bm_mem_arch_v2_prim_3_b1_chk0_col_0_b2_mextd_arch_v2_c1_ram1_v2_d2048_by9_newSim8))
+ )
+ )
+ (net (rename N9 "dina<0>")
+ (joined
+ (portRef dina_0_)
+ (portRef DIA_0_ (instanceRef async_fifo_8_8_128_fifo_generator_v2_2_xst_1_blkmemdp_v6_2_xst_bm_mem_arch_v2_prim_3_b1_chk0_col_0_b2_mextd_arch_v2_c1_ram1_v2_d2048_by9_newSim8))
+ )
+ )
+ (net (rename N19 "enb")
+ (joined
+ (portRef enb)
+ (portRef ENB (instanceRef async_fifo_8_8_128_fifo_generator_v2_2_xst_1_blkmemdp_v6_2_xst_bm_mem_arch_v2_prim_3_b1_chk0_col_0_b2_mextd_arch_v2_c1_ram1_v2_d2048_by9_newSim8))
+ )
+ )
+ (net (rename N20 "wea")
+ (joined
+ (portRef wea)
+ (portRef WEA (instanceRef async_fifo_8_8_128_fifo_generator_v2_2_xst_1_blkmemdp_v6_2_xst_bm_mem_arch_v2_prim_3_b1_chk0_col_0_b2_mextd_arch_v2_c1_ram1_v2_d2048_by9_newSim8))
+ )
+ )
+ (net (rename N22 "sinita")
+ (joined
+ (portRef sinita)
+ (portRef SSRA (instanceRef async_fifo_8_8_128_fifo_generator_v2_2_xst_1_blkmemdp_v6_2_xst_bm_mem_arch_v2_prim_3_b1_chk0_col_0_b2_mextd_arch_v2_c1_ram1_v2_d2048_by9_newSim8))
+ )
+ )
+ (net (rename N23 "sinitb")
+ (joined
+ (portRef sinitb)
+ (portRef SSRB (instanceRef async_fifo_8_8_128_fifo_generator_v2_2_xst_1_blkmemdp_v6_2_xst_bm_mem_arch_v2_prim_3_b1_chk0_col_0_b2_mextd_arch_v2_c1_ram1_v2_d2048_by9_newSim8))
+ )
+ )
+ (net (rename N26 "clka")
+ (joined
+ (portRef clka)
+ (portRef CLKA (instanceRef async_fifo_8_8_128_fifo_generator_v2_2_xst_1_blkmemdp_v6_2_xst_bm_mem_arch_v2_prim_3_b1_chk0_col_0_b2_mextd_arch_v2_c1_ram1_v2_d2048_by9_newSim8))
+ )
+ )
+ (net (rename N27 "clkb")
+ (joined
+ (portRef clkb)
+ (portRef CLKB (instanceRef async_fifo_8_8_128_fifo_generator_v2_2_xst_1_blkmemdp_v6_2_xst_bm_mem_arch_v2_prim_3_b1_chk0_col_0_b2_mextd_arch_v2_c1_ram1_v2_d2048_by9_newSim8))
+ )
+ )
+ (net (rename N28 "addra<6>")
+ (joined
+ (portRef addra_6_)
+ (portRef ADDRA_6_ (instanceRef async_fifo_8_8_128_fifo_generator_v2_2_xst_1_blkmemdp_v6_2_xst_bm_mem_arch_v2_prim_3_b1_chk0_col_0_b2_mextd_arch_v2_c1_ram1_v2_d2048_by9_newSim8))
+ )
+ )
+ (net (rename N29 "addra<5>")
+ (joined
+ (portRef addra_5_)
+ (portRef ADDRA_5_ (instanceRef async_fifo_8_8_128_fifo_generator_v2_2_xst_1_blkmemdp_v6_2_xst_bm_mem_arch_v2_prim_3_b1_chk0_col_0_b2_mextd_arch_v2_c1_ram1_v2_d2048_by9_newSim8))
+ )
+ )
+ (net (rename N30 "addra<4>")
+ (joined
+ (portRef addra_4_)
+ (portRef ADDRA_4_ (instanceRef async_fifo_8_8_128_fifo_generator_v2_2_xst_1_blkmemdp_v6_2_xst_bm_mem_arch_v2_prim_3_b1_chk0_col_0_b2_mextd_arch_v2_c1_ram1_v2_d2048_by9_newSim8))
+ )
+ )
+ (net (rename N31 "addra<3>")
+ (joined
+ (portRef addra_3_)
+ (portRef ADDRA_3_ (instanceRef async_fifo_8_8_128_fifo_generator_v2_2_xst_1_blkmemdp_v6_2_xst_bm_mem_arch_v2_prim_3_b1_chk0_col_0_b2_mextd_arch_v2_c1_ram1_v2_d2048_by9_newSim8))
+ )
+ )
+ (net (rename N32 "addra<2>")
+ (joined
+ (portRef addra_2_)
+ (portRef ADDRA_2_ (instanceRef async_fifo_8_8_128_fifo_generator_v2_2_xst_1_blkmemdp_v6_2_xst_bm_mem_arch_v2_prim_3_b1_chk0_col_0_b2_mextd_arch_v2_c1_ram1_v2_d2048_by9_newSim8))
+ )
+ )
+ (net (rename N33 "addra<1>")
+ (joined
+ (portRef addra_1_)
+ (portRef ADDRA_1_ (instanceRef async_fifo_8_8_128_fifo_generator_v2_2_xst_1_blkmemdp_v6_2_xst_bm_mem_arch_v2_prim_3_b1_chk0_col_0_b2_mextd_arch_v2_c1_ram1_v2_d2048_by9_newSim8))
+ )
+ )
+ (net (rename N34 "addra<0>")
+ (joined
+ (portRef addra_0_)
+ (portRef ADDRA_0_ (instanceRef async_fifo_8_8_128_fifo_generator_v2_2_xst_1_blkmemdp_v6_2_xst_bm_mem_arch_v2_prim_3_b1_chk0_col_0_b2_mextd_arch_v2_c1_ram1_v2_d2048_by9_newSim8))
+ )
+ )
+ (net (rename N35 "addrb<6>")
+ (joined
+ (portRef addrb_6_)
+ (portRef ADDRB_6_ (instanceRef async_fifo_8_8_128_fifo_generator_v2_2_xst_1_blkmemdp_v6_2_xst_bm_mem_arch_v2_prim_3_b1_chk0_col_0_b2_mextd_arch_v2_c1_ram1_v2_d2048_by9_newSim8))
+ )
+ )
+ (net (rename N36 "addrb<5>")
+ (joined
+ (portRef addrb_5_)
+ (portRef ADDRB_5_ (instanceRef async_fifo_8_8_128_fifo_generator_v2_2_xst_1_blkmemdp_v6_2_xst_bm_mem_arch_v2_prim_3_b1_chk0_col_0_b2_mextd_arch_v2_c1_ram1_v2_d2048_by9_newSim8))
+ )
+ )
+ (net (rename N37 "addrb<4>")
+ (joined
+ (portRef addrb_4_)
+ (portRef ADDRB_4_ (instanceRef async_fifo_8_8_128_fifo_generator_v2_2_xst_1_blkmemdp_v6_2_xst_bm_mem_arch_v2_prim_3_b1_chk0_col_0_b2_mextd_arch_v2_c1_ram1_v2_d2048_by9_newSim8))
+ )
+ )
+ (net (rename N38 "addrb<3>")
+ (joined
+ (portRef addrb_3_)
+ (portRef ADDRB_3_ (instanceRef async_fifo_8_8_128_fifo_generator_v2_2_xst_1_blkmemdp_v6_2_xst_bm_mem_arch_v2_prim_3_b1_chk0_col_0_b2_mextd_arch_v2_c1_ram1_v2_d2048_by9_newSim8))
+ )
+ )
+ (net (rename N39 "addrb<2>")
+ (joined
+ (portRef addrb_2_)
+ (portRef ADDRB_2_ (instanceRef async_fifo_8_8_128_fifo_generator_v2_2_xst_1_blkmemdp_v6_2_xst_bm_mem_arch_v2_prim_3_b1_chk0_col_0_b2_mextd_arch_v2_c1_ram1_v2_d2048_by9_newSim8))
+ )
+ )
+ (net (rename N40 "addrb<1>")
+ (joined
+ (portRef addrb_1_)
+ (portRef ADDRB_1_ (instanceRef async_fifo_8_8_128_fifo_generator_v2_2_xst_1_blkmemdp_v6_2_xst_bm_mem_arch_v2_prim_3_b1_chk0_col_0_b2_mextd_arch_v2_c1_ram1_v2_d2048_by9_newSim8))
+ )
+ )
+ (net (rename N41 "addrb<0>")
+ (joined
+ (portRef addrb_0_)
+ (portRef ADDRB_0_ (instanceRef async_fifo_8_8_128_fifo_generator_v2_2_xst_1_blkmemdp_v6_2_xst_bm_mem_arch_v2_prim_3_b1_chk0_col_0_b2_mextd_arch_v2_c1_ram1_v2_d2048_by9_newSim8))
+ )
+ )
+ (net (rename N54 "doutb<7>")
+ (joined
+ (portRef doutb_7_)
+ (portRef DOB_7_ (instanceRef async_fifo_8_8_128_fifo_generator_v2_2_xst_1_blkmemdp_v6_2_xst_bm_mem_arch_v2_prim_3_b1_chk0_col_0_b2_mextd_arch_v2_c1_ram1_v2_d2048_by9_newSim8))
+ )
+ )
+ (net (rename N55 "doutb<6>")
+ (joined
+ (portRef doutb_6_)
+ (portRef DOB_6_ (instanceRef async_fifo_8_8_128_fifo_generator_v2_2_xst_1_blkmemdp_v6_2_xst_bm_mem_arch_v2_prim_3_b1_chk0_col_0_b2_mextd_arch_v2_c1_ram1_v2_d2048_by9_newSim8))
+ )
+ )
+ (net (rename N56 "doutb<5>")
+ (joined
+ (portRef doutb_5_)
+ (portRef DOB_5_ (instanceRef async_fifo_8_8_128_fifo_generator_v2_2_xst_1_blkmemdp_v6_2_xst_bm_mem_arch_v2_prim_3_b1_chk0_col_0_b2_mextd_arch_v2_c1_ram1_v2_d2048_by9_newSim8))
+ )
+ )
+ (net (rename N57 "doutb<4>")
+ (joined
+ (portRef doutb_4_)
+ (portRef DOB_4_ (instanceRef async_fifo_8_8_128_fifo_generator_v2_2_xst_1_blkmemdp_v6_2_xst_bm_mem_arch_v2_prim_3_b1_chk0_col_0_b2_mextd_arch_v2_c1_ram1_v2_d2048_by9_newSim8))
+ )
+ )
+ (net (rename N58 "doutb<3>")
+ (joined
+ (portRef doutb_3_)
+ (portRef DOB_3_ (instanceRef async_fifo_8_8_128_fifo_generator_v2_2_xst_1_blkmemdp_v6_2_xst_bm_mem_arch_v2_prim_3_b1_chk0_col_0_b2_mextd_arch_v2_c1_ram1_v2_d2048_by9_newSim8))
+ )
+ )
+ (net (rename N59 "doutb<2>")
+ (joined
+ (portRef doutb_2_)
+ (portRef DOB_2_ (instanceRef async_fifo_8_8_128_fifo_generator_v2_2_xst_1_blkmemdp_v6_2_xst_bm_mem_arch_v2_prim_3_b1_chk0_col_0_b2_mextd_arch_v2_c1_ram1_v2_d2048_by9_newSim8))
+ )
+ )
+ (net (rename N60 "doutb<1>")
+ (joined
+ (portRef doutb_1_)
+ (portRef DOB_1_ (instanceRef async_fifo_8_8_128_fifo_generator_v2_2_xst_1_blkmemdp_v6_2_xst_bm_mem_arch_v2_prim_3_b1_chk0_col_0_b2_mextd_arch_v2_c1_ram1_v2_d2048_by9_newSim8))
+ )
+ )
+ (net (rename N61 "doutb<0>")
+ (joined
+ (portRef doutb_0_)
+ (portRef DOB_0_ (instanceRef async_fifo_8_8_128_fifo_generator_v2_2_xst_1_blkmemdp_v6_2_xst_bm_mem_arch_v2_prim_3_b1_chk0_col_0_b2_mextd_arch_v2_c1_ram1_v2_d2048_by9_newSim8))
+ )
+ )
+))))
+(design async_fifo_8_8_128_fifo_generator_v2_2_xst_1_blkmemdp_v6_2_xst (cellRef async_fifo_8_8_128_fifo_generator_v2_2_xst_1_blkmemdp_v6_2_xst (libraryRef test_lib))
+ (property X_CORE_INFO (string "null"))
+ (property PART (string "XC2VP20-6-ff896") (owner "Xilinx")))
+)
projects / fleet.git / blobdiff