migrate jelib->delib

[fleet.git] / chips / marina / electric / centersJ.delib / ctrAND1in100.lay

diff --git a/chips/marina/electric/centersJ.delib/ctrAND1in100.lay b/chips/marina/electric/centersJ.delib/ctrAND1in100.lay
new file mode 100644 (file)
index 0000000..3235097
--- /dev/null
+++ b/chips/marina/electric/centersJ.delib/ctrAND1in100.lay
@@ -0,0 +1,39 @@
+HcentersJ|8.10k
+
+# External Libraries:
+
+Lgates1inM|gates1inM
+
+# Cell ctrAND1in100;1{lay}
+CctrAND1in100;1{lay}||cmos90|1231629883946|1240848417057||ATTR_NCC(D5G3;NTY70;)S["exportsConnectedByParent vdd /vdd_[0-9]+/"]
+Ngeneric:Facet-Center|art@0||0|0||||AV
+Igates1inM:inv10D;1{lay}|inv10D@1||-36|0|||D5G4;
+Igates1inM:inv30;1{lay}|inv30@1||-11|0|||D5G4;
+Igates1inM:inv100;3{lay}|inv100@0||50|0|||D5G4;
+NMetal-1-Pin|pin@0||-30|25||||
+NMetal-1-Pin|pin@1||-30|-25||||
+NMetal-1-Pin|pin@4||1|25||||
+NMetal-1-Pin|pin@5||1|-25||||
+Ametal-2|net@7|||S0|inv30@1|gnd|-27.5|0|inv10D@1|gnd_1|-27.5|0
+Ametal-2|net@8|||S0|inv30@1|vdd|-27.5|50|inv10D@1|vdd_2|-27.5|50
+Ametal-2|net@9|||S0|inv30@1|vdd_1|-27.5|-50|inv10D@1|vdd_3|-27.5|-50
+Ametal-1|net@10|||S0|inv30@1|inB|-18|25|pin@0||-30|25
+Ametal-1|net@11|||S900|pin@0||-30|25|inv10D@1|out|-30|7
+Ametal-1|net@12|||S0|inv30@1|inA|-18|-25|pin@1||-30|-25
+Ametal-1|net@13|||S2700|pin@1||-30|-25|inv10D@1|out|-30|7
+Ametal-2|net@17|||S0|inv100@0|gnd_2|5.5|0|inv30@1|gnd_1|5.5|0
+Ametal-2|net@18|||S0|inv100@0|vdd_4|5.5|50|inv30@1|vdd_2|5.5|50
+Ametal-2|net@19|||S0|inv100@0|vdd_5|5.5|-50|inv30@1|vdd_3|5.5|-50
+Ametal-1|net@20|||S2700|inv30@1|out|1|0|pin@4||1|25
+Ametal-1|net@21|||S1800|pin@4||1|25|inv100@0|in_1|13|25
+Ametal-1|net@22|||S900|inv30@1|out|1|0|pin@5||1|-25
+Ametal-1|net@23|||S1800|pin@5||1|-25|inv100@0|in|13|-25
+Egnd||D5G2;|inv10D@1|gnd|G
+Egnd_1||D5G2;|inv100@0|gnd_1|G
+Ein||D5G2;|inv10D@1|in|I
+Eout_1|out|D5G2;|inv100@0|out|O
+Evdd||D5G2;|inv10D@1|vdd|P
+Evdd_1||D5G2;|inv10D@1|vdd_1|P
+Evdd_2||D5G2;|inv100@0|vdd_2|P
+Evdd_3||D5G2;|inv100@0|vdd_3|P
+X