migrate jelib->delib
[fleet.git] / chips / marina / electric / centersJ.delib / ctrAND3in100.lay
diff --git a/chips/marina/electric/centersJ.delib/ctrAND3in100.lay b/chips/marina/electric/centersJ.delib/ctrAND3in100.lay
new file mode 100644 (file)
index 0000000..a68d1a7
--- /dev/null
@@ -0,0 +1,49 @@
+HcentersJ|8.10k
+
+# External Libraries:
+
+Lgates1inM|gates1inM
+
+Lgates3inM|gates3inM
+
+LwiresL|wiresL
+
+# Cell ctrAND3in100;2{lay}
+CctrAND3in100;2{lay}||cmos90|1195149611468|1238257435226||ATTR_NCC(D5G3;NTY70;)S["exportsConnectedByParent vdd /vdd_[0-9]+/"]
+Ngeneric:Facet-Center|art@0||0|0||||AV
+Igates1inM:inv40;2{lay}|inv40@1||-21|0|||D5G4;
+Igates1inM:inv100;3{lay}|inv100@2||35|0|||D5G4;
+Igates3inM:nor3in14;3{lay}|nor3in14@1||-103.5|0|||D5G4;
+NMetal-1-Pin|pin@0||-5|-25||||
+NMetal-1-Pin|pin@1||-5|25||||
+NMetal-1-Pin|pin@15||-34|-18||||
+NMetal-1-Pin|pin@27||-52|25||||
+IwiresL:wellContacts26;1{lay}|wellCont@2||-46|0|||D5G4;
+Ametal-1|net@6|||S900|inv40@1|out_1|-5|-16|pin@0||-5|-25
+Ametal-1|net@7|||S1800|pin@0||-5|-25|inv100@2|in|-2|-25
+Ametal-1|net@8|||S2700|inv40@1|out|-5|16|pin@1||-5|25
+Ametal-1|net@9|||S1800|pin@1||-5|25|inv100@2|in_1|-2|25
+Ametal-1|net@38||0.4|S900|pin@15||-34|-18|inv40@1|in|-34|-25
+Ametal-2|net@52||6.2|S0|inv40@1|vdd_2|-0.5|50|inv100@2|vdd_4|-9.5|50
+Ametal-2|net@53||6.2|S1800|inv100@2|gnd_2|-9.5|0|inv40@1|gnd_1|-0.5|0
+Ametal-2|net@54||6.2|S1800|inv100@2|vdd_5|-9.5|-50|inv40@1|vdd_3|-0.5|-50
+Ametal-1|net@57||0.4|S2700|nor3in14@1|out|-52|-18|pin@27||-52|25
+Ametal-2|net@61|||S0|wellCont@2|gnd_1|-41.5|0|inv40@1|gnd|-41.5|0
+Ametal-2|net@62|||S0|wellCont@2|vdd_2|-41.5|-50|inv40@1|vdd_1|-41.5|-50
+Ametal-2|net@63|||S0|wellCont@2|vdd_3|-41.5|50|inv40@1|vdd|-41.5|50
+Ametal-2|net@74|||S0|nor3in14@1|gnd_1|-50.5|0|wellCont@2|gnd|-50.5|0
+Ametal-2|net@75|||S0|nor3in14@1|vdd_3|-50.5|-50|wellCont@2|vdd|-50.5|-50
+Ametal-2|net@76|||S0|nor3in14@1|vdd_2|-50.5|50|wellCont@2|vdd_1|-50.5|50
+Ametal-1|net@82||0.4|S0|inv40@1|in_1|-34|25|pin@27||-52|25
+Ametal-1|net@83||0.4|S0|pin@15||-34|-18|nor3in14@1|out|-52|-18
+Egnd||D5G2;|nor3in14@1|gnd|G
+Egnd_1||D5G2;|inv100@2|gnd_1|G
+EinA||D5G2;|nor3in14@1|inA|I
+EinB||D5G2;|nor3in14@1|inB|O
+EinC||D5G2;|nor3in14@1|inC|I
+Eout||D5G2;|inv100@2|out|O
+Evdd||D5G2;|nor3in14@1|vdd|P
+Evdd_1||D5G2;|nor3in14@1|vdd_1|P
+Evdd_2||D5G2;|inv100@2|vdd_2|P
+Evdd_3||D5G2;|inv100@2|vdd_3|P
+X