migrate jelib->delib

[fleet.git] / chips / marina / electric / compareM.delib / countComp.sch

diff --git a/chips/marina/electric/compareM.delib/countComp.sch b/chips/marina/electric/compareM.delib/countComp.sch
new file mode 100644 (file)
index 0000000..d13f468
--- /dev/null
+++ b/chips/marina/electric/compareM.delib/countComp.sch
@@ -0,0 +1,91 @@
+HcompareM|8.10k
+
+# External Libraries:
+
+LorangeTSMC090nm|orangeTSMC090nm
+
+LscanM|scanM
+
+LwiresL|wiresL
+
+# Cell countComp;1{sch}
+CcountComp;1{sch}||schematic|1242046613932|1243246631749|I
+Ngeneric:Facet-Center|art@0||0|0||||AV
+IcompareTree;1{ic}|compareT@0||29|0|||D5G4;
+NOff-Page|conn@0||25|-12|||R|
+NOff-Page|conn@1||33|-11|||R|
+NOff-Page|conn@4||-12|9||||
+NOff-Page|conn@6||-30|-15|||YRRR|
+NOff-Page|conn@7||-30|10|||R|
+NOff-Page|conn@8||-13|3||||
+NOff-Page|conn@10||0|-11|||RRR|
+NOff-Page|conn@11||45|-7|||YRRR|
+NOff-Page|conn@12||45|10|||R|
+NOff-Page|conn@13||54|1||||
+IcountComp;1{ic}|countCom@0||43|24.5|||D5G4;
+IcountCompGasP;1{ic}|countCom@1||0|2|||D5G4;
+Ngeneric:Invisible-Pin|pin@0||11.5|25.5|||||ART_message(D5G3;)Sies 18 May 2009
+Ngeneric:Invisible-Pin|pin@1||12.5|31.5|||||ART_message(D5G6;)ScountComp
+NBus_Pin|pin@5||3|16|-1|-1||
+NWire_Pin|pin@51||-22|-10||||
+NWire_Pin|pin@52||-22|-13||||
+NWire_Pin|pin@53||-22|-6||||
+NWire_Pin|pin@54||-22|-4||||
+NWire_Pin|pin@55||-22|-1||||
+NWire_Pin|pin@57||-22|1.5||||
+NWire_Pin|pin@58||-39|-8||||
+NWire_Pin|pin@59||-39|19||||
+NWire_Pin|pin@60||-3|19||||
+NBus_Pin|pin@66||-8|6|-1|-1||
+NBus_Pin|pin@67||-8|8|-1|-1||
+NBus_Pin|pin@72||19|4|-1|-1||
+NBus_Pin|pin@73||19|8|-1|-1||
+NBus_Pin|pin@74||29|8|-1|-1||
+IscanM:scanEx3;1{ic}|scanEx3@0||-30|-2|X||D5G4;
+IscanM:scanFx1tall;1{ic}|scanFx1t@0||45|2|||D5G4;
+IwiresL:tranCap;1{ic}|tc[1:11]|D5G3;Y4;|15|17|||D5G4;
+IorangeTSMC090nm:wire90;1{ic}|wire90@0||9|-2|Y||D0G4;|ATTR_L(D5G1;PUD)S958|ATTR_LEWIRE(P)I1|ATTR_layer(D5G1;NPY-1;)I1|ATTR_width(D5G1;NPY-2;)I3
+IorangeTSMC090nm:wire90;1{ic}|wire90@1||9|2|Y||D0G4;|ATTR_L(D5G1;PUD)S958|ATTR_LEWIRE(P)I1|ATTR_layer(D5G1;NPY-1;)I1|ATTR_width(D5G1;NPY-2;)I3
+IorangeTSMC090nm:wire90;1{ic}|wire90@2||19|0|Y||D0G4;|ATTR_L(D5G1;PUD)S958|ATTR_LEWIRE(P)I1|ATTR_layer(D5G1;NPY-1;)I1|ATTR_width(D5G1;NPY-2;)I3
+Awire|go|D8G2;||0|compareT@0|go|23|2|wire90@1|b|11.5|2
+Awire|goLO[1]|D8G2;||1800|countCom@1|goLO[1]|5|0|wire90@2|a|16.5|0
+Awire|mc|D5G2;||2700|countCom@1|mc|-3|8|pin@60||-3|19
+Abus|net@65||-0.5|IJ2700|conn@6|y|-30|-13|scanEx3@0|sir[1:9]|-30|-10
+Abus|net@66||-0.5|IJ2700|scanEx3@0|sor[1:9]|-30|5.5|conn@7|a|-30|8
+Awire|net@67|||1800|scanEx3@0|dIn[1]|-25|-10|pin@51||-22|-10
+Awire|net@71|||0|pin@54||-22|-4|scanEx3@0|dIn[2]|-25|-4
+Awire|net@73|||0|pin@57||-22|1.5|scanEx3@0|dIn[3]|-25|1.5
+Awire|net@76|||0|scanEx3@0|mc|-35|-8|pin@58||-39|-8
+Awire|net@77|||2700|pin@58||-39|-8|pin@59||-39|19
+Awire|net@78|||1800|pin@59||-39|19|pin@60||-3|19
+Abus|net@96||-0.5|IJ0|countCom@1|pred[A,B]|-5|6|pin@66||-8|6
+Abus|net@105||-0.5|IJ1800|countCom@1|in[L,E,G]|5|4|pin@72||19|4
+Abus|net@106||-0.5|IJ2700|pin@72||19|4|pin@73||19|8
+Abus|net@107||-0.5|IJ1800|pin@73||19|8|pin@74||29|8
+Abus|net@109||-0.5|IJ900|compareT@0|inB[1:37]|33|-4|conn@1|y|33|-9
+Abus|net@110||-0.5|IJ2700|conn@0|y|25|-10|compareT@0|inA[1:37]|25|-4
+Awire|net@118|||0|wire90@0|a|6.5|-2|countCom@1|ready|5|-2
+Awire|net@119|||0|compareT@0|goLO[1]|23|0|wire90@2|b|21.5|0
+Awire|net@124|||0|wire90@1|a|6.5|2|countCom@1|go|5|2
+Abus|net@125||-0.5|IJ900|countCom@1|s[4:6]|0|-4|conn@10|a|0|-9
+Abus|net@126||-0.5|IJ2700|conn@11|y|45|-5|scanFx1t@0|sic[1:9]|45|0
+Abus|net@127||-0.5|IJ2700|scanFx1t@0|soc[1:9]|45|4|conn@12|a|45|8
+Awire|net@128|||0|conn@13|a|52|1|scanFx1t@0|dout[1]|50|1
+Abus|pred[A,B]|D5G2;|-0.5|IJ2700|pin@66||-8|6|pin@67||-8|8
+Awire|ready|D8G2;||1800|wire90@0|b|11.5|-2|compareT@0|ready|23|-2
+Abus|s[1:3]|D5G2;|-0.5|IJ900|pin@5||3|16|countCom@1|s[1:3]|3|8
+Awire|s[1]|D5G2;||900|pin@51||-22|-10|pin@52||-22|-13
+Awire|s[2]|D5G2;||2700|pin@53||-22|-6|pin@54||-22|-4
+Awire|s[3]|D5G2;||900|pin@57||-22|1.5|pin@55||-22|-1
+Abus|val[L,E,G]|D5G2;|-0.5|IJ900|pin@74||29|8|compareT@0|out[1][L,E,G]|29|4
+Etake[A,B]|count[L,E,G]|D6G2;|conn@10|y|O
+Edout[1]||D6G2;|conn@13|y|O
+EinA[1:37]||D4G2;|conn@0|a|I
+EinB[1:37]||D4G2;|conn@1|a|I
+Epred[A]||D4G2;|conn@4|a|I
+Epred[B]||D4G2;|conn@8|a|I
+Esic[1:9]||D4G2;|conn@11|a|B
+Esir[1:9]||D4G2;|conn@6|a|I
+Esoc[1:9]||D6G2;|conn@12|y|B
+Esor[1:9]||D6G2;|conn@7|y|O
+X