migrate jelib->delib

[fleet.git] / chips / marina / electric / compareM.delib / gaspCompareHalf.lay

diff --git a/chips/marina/electric/compareM.delib/gaspCompareHalf.lay b/chips/marina/electric/compareM.delib/gaspCompareHalf.lay
new file mode 100644 (file)
index 0000000..884fc4b
--- /dev/null
+++ b/chips/marina/electric/compareM.delib/gaspCompareHalf.lay
@@ -0,0 +1,81 @@
+HcompareM|8.10k
+
+# External Libraries:
+
+LdriversM|driversM
+
+Lgates1inM|gates1inM
+
+Lgates2inM|gates2inM
+
+LwiresL|wiresL
+
+# Cell gaspCompareHalf;1{lay}
+CgaspCompareHalf;1{lay}||cmos90|1242068284442|1243246631749|I|ATTR_NCC(D5G3;NTY70;)S["exportsConnectedByParent vdd /vdd_[0-9]+/"]|DRC_last_good_drc_bit()I10|DRC_last_good_drc_date()G1242094434355
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NX-Metal-1-Metal-2-Con|contact@0||-123.5|-22||||
+NX-Metal-1-Metal-2-Con|contact@1||-68.5|-22||||
+NX-Metal-1-Metal-2-Con|contact@2||40.5|-22||||
+NX-Metal-1-Metal-2-Con|contact@3||114.5|-22||||
+NX-Metal-1-Metal-2-Con|contact@4||-155.5|10||||
+NX-Metal-1-Metal-2-Con|contact@5||175.5|16||||
+Igates1inM:inv510;3{lay}|inv510@0||-173|0|X||D5G4;
+IdriversM:latchDriver60;1{lay}|latchDri@0||72|0|||D5G4;
+Igates2inM:nor10sym;2{lay}|nor10sym@0||9.5|0|||D5G4;
+Igates2inM:nor20;1{lay}|nor20@0||-54.5|0|||D5G4;
+NMetal-1-Pin|pin@0||1|24.5||||
+NMetal-2-Pin|pin@2||-141.5|10||||
+NMetal-2-Pin|pin@4||163.5|16||||
+IdriversM:predDri60wMC;1{lay}|predDri6@0||-123.5|0|||D5G4;
+IdriversM:sucDri60;1{lay}|sucDri60@0||147.5|0|||D5G4;
+IwiresL:wellContacts13;1{lay}|wellCont@0||-17.5|0|||D5G4;
+Ametal-2|net@3|||S0|nor20@0|gnd|-87|0|predDri6@0|gnd_1|-87|0
+Ametal-2|net@4|||S0|nor20@0|vdd|-87|50|predDri6@0|vdd_2|-87|50
+Ametal-2|net@5|||S0|nor20@0|vdd_1|-87|-50|predDri6@0|vdd_3|-87|-50
+Ametal-2|net@6|||S1800|latchDri@0|gnd|105|0|sucDri60@0|gnd|107|0
+Ametal-2|net@7|||S1800|latchDri@0|vdd|105|50|sucDri60@0|vdd|107|50
+Ametal-2|net@8|||S1800|latchDri@0|vdd_5|105|-50|sucDri60@0|vdd_1|107|-50
+Ametal-2|net@9|||S0|nor10sym@0|gnd|-13|0|wellCont@0|gnd_1|-13|0
+Ametal-2|net@10|||S0|nor10sym@0|vdd_1|-13|-50|wellCont@0|vdd_2|-13|-50
+Ametal-2|net@11|||S0|nor10sym@0|vdd|-13|50|wellCont@0|vdd_3|-13|50
+Ametal-2|net@12|||S0|nor20@0|gnd_1|-22|0|wellCont@0|gnd|-22|0
+Ametal-2|net@13|||S0|nor20@0|vdd_3|-22|-50|wellCont@0|vdd|-22|-50
+Ametal-2|net@14|||S0|nor20@0|vdd_2|-22|50|wellCont@0|vdd_1|-22|50
+Ametal-1|net@15|||S900|predDri6@0|in|-123.5|-19|contact@0||-123.5|-22
+Ametal-2|net@17|||S1800|contact@0||-123.5|-22|contact@1||-68.5|-22
+Ametal-1|net@18||0.4|S900|nor20@0|out_1|-68.5|-17.5|contact@1||-68.5|-22
+Ametal-2|net@19|||S1800|contact@1||-68.5|-22|contact@2||40.5|-22
+Ametal-1|net@20|||S2700|latchDri@0|in|40.5|-25|contact@2||40.5|-22
+Ametal-2|net@21|||S1800|contact@2||40.5|-22|contact@3||114.5|-22
+Ametal-1|net@22|||S2700|sucDri60@0|in|114.5|-25|contact@3||114.5|-22
+Ametal-1|net@23|||S1800|nor20@0|inB|-46|24.5|pin@0||1|24.5
+Ametal-1|net@24|||S900|pin@0||1|24.5|nor10sym@0|out_2|1|23
+Ametal-1|net@26|||S2700|predDri6@0|pred|-155.5|7|contact@4||-155.5|10
+Ametal-2|net@27|||S1800|contact@4||-155.5|10|pin@2||-141.5|10
+Ametal-2|net@28|||S0|inv510@0|gnd|-160|0|predDri6@0|gnd|-160|0
+Ametal-2|net@29|||S0|inv510@0|vdd|-160|50|predDri6@0|vdd|-160|50
+Ametal-2|net@30|||S0|inv510@0|vdd_1|-160|-50|predDri6@0|vdd_1|-160|-50
+Ametal-2|net@31||6.2|S1800|nor10sym@0|vdd_3|32|-50|latchDri@0|vdd_7|36.5|-50
+Ametal-2|net@32||6.2|S0|latchDri@0|gnd_1|36.5|0|nor10sym@0|gnd_1|32|0
+Ametal-2|net@33||6.2|S0|latchDri@0|vdd_8|36.5|50|nor10sym@0|vdd_2|32|50
+Ametal-1|net@34|||S900|sucDri60@0|succ|175.5|32|contact@5||175.5|16
+Ametal-2|net@35|||S0|contact@5||175.5|16|pin@4||163.5|16
+Ametal-1|net@39|||S1800|inv510@0|in[1]|-167|7|predDri6@0|pred|-155.5|7
+EinA@251495090|fireLO|D5G2;|nor20@0|inA|I
+Egnd_2|gnd|D5G2;|inv510@0|gnd_1|G
+Egnd_1||D5G2;|sucDri60@0|gnd_1|G
+EinLO[X]||D5G2;|pin@0||I
+EinB|in[E]|D5G2;|nor10sym@0|inB|I
+EinA|in[X]|D5G2;|nor10sym@0|inA|I
+Emc||D5G2;|predDri6@0|mc|I
+Epred[X]||D5G2;|pin@2||U
+Ein[1]|pred[X_1]|D5G2;|inv510@0|in[1]|I
+Eout10|s[1]|D5G2;|inv510@0|out10|O
+Esucc[X]||D5G2;|pin@4||U
+Esucc_1|succ[X_1]|D5G2;|sucDri60@0|succ_1|O
+Eout|take[X]|D5G2;|latchDri@0|out|O
+Evdd_4|vdd|D5G2;|inv510@0|vdd_2|P
+Evdd_2||D5G2;|sucDri60@0|vdd_2|P
+Evdd_3||D5G2;|sucDri60@0|vdd_3|P
+Evdd_5||D5G2;|inv510@0|vdd_3|P
+X