migrate jelib->delib

[fleet.git] / chips / marina / electric / compareM.delib / leafB.lay

diff --git a/chips/marina/electric/compareM.delib/leafB.lay b/chips/marina/electric/compareM.delib/leafB.lay
new file mode 100644 (file)
index 0000000..083335c
--- /dev/null
+++ b/chips/marina/electric/compareM.delib/leafB.lay
@@ -0,0 +1,34 @@
+HcompareM|8.10k
+
+# External Libraries:
+
+LwiresL|wiresL
+
+# Cell leafB;1{lay}
+CleafB;1{lay}||cmos90|1242261116092|1243246631749|I|ATTR_NCC(D5G3;NTY70;)S["exportsConnectedByParent vdd /vdd_[0-9]+/"]|DRC_last_good_drc_bit()I10|DRC_last_good_drc_date()G1243262533078
+Ngeneric:Facet-Center|art@0||0|0||||AV
+Inor05twin;2{lay}|nor05twi@0||-33|0|||D5G4;
+IwiresL:wellContacts13;1{lay}|wellCont@0||-6|0|||D5G4;
+Ixor5;1{lay}|xor5@0||27|0|||D5G4;
+Ametal-2|net@0|||S0|wellCont@0|gnd|-10.5|0|nor05twi@0|gnd_1|-12.5|0
+Ametal-2|net@1|||S0|wellCont@0|vdd|-10.5|-50|nor05twi@0|vdd_3|-12.5|-50
+Ametal-2|net@2|||S0|wellCont@0|vdd_1|-10.5|50|nor05twi@0|vdd_2|-12.5|50
+Ametal-2|net@3|||S1800|wellCont@0|gnd_1|-1.5|0|xor5@0|gnd|0.5|0
+Ametal-2|net@4|||S1800|wellCont@0|vdd_3|-1.5|50|xor5@0|vdd|0.5|50
+Ametal-2|net@5|||S1800|wellCont@0|vdd_2|-1.5|-50|xor5@0|vdd_1|0.5|-50
+Ametal-2|net@6|||S1800|nor05twi@0|inB[F]|-13|22|xor5@0|b[F]|1|22
+Ametal-2|net@7|||S0|xor5@0|a[F]|1|28|nor05twi@0|inA[F]|-13|28
+Ametal-2|net@8|||S0|xor5@0|a[T_1]|1|-28|nor05twi@0|a[T]|-13|-28
+Ametal-2|net@9|||S0|xor5@0|b[T_1]|1|-22|nor05twi@0|b[T]|-13|-22
+Ea[T]||D5G2;|xor5@0|a[T]|I
+Eb[T]||D5G2;|xor5@0|b[T]|I
+Egnd||D5G2;|nor05twi@0|gnd|G
+Egnd_1||D5G2;X2.5;|xor5@0|gnd_1|G
+Eout[E]||D5G2;|xor5@0|out[E]|I
+Eout[G]||D5G2;|nor05twi@0|out[G]|O
+Eout[L]||D5G2;|nor05twi@0|out[L]|O
+Evdd||D5G2;|nor05twi@0|vdd|P
+Evdd_1||D5G2;|nor05twi@0|vdd_1|P
+Evdd_2||D5G2;X2.5;|xor5@0|vdd_2|P
+Evdd_3||D5G2;X2.5;|xor5@0|vdd_3|P
+X