migrate jelib->delib

[fleet.git] / chips / marina / electric / coversM.delib / fill2x2.lay

diff --git a/chips/marina/electric/coversM.delib/fill2x2.lay b/chips/marina/electric/coversM.delib/fill2x2.lay
new file mode 100644 (file)
index 0000000..4d86adc
--- /dev/null
+++ b/chips/marina/electric/coversM.delib/fill2x2.lay
@@ -0,0 +1,68 @@
+HcoversM|8.10k
+
+# External Libraries:
+
+LfillM|fillM
+
+# Cell fill2x2;1{lay}
+Cfill2x2;1{lay}||cmos90|1239375826715|1239549868233|
+Ngeneric:Facet-Center|art@0||0|0||||AV
+IfillM:fillAllGNDctr;1{lay}|fillAllG@0||-72|72|||D5G4;
+IfillM:fillAllGNDctr;1{lay}|fillAllG@1||-72|-72|||D5G4;
+IfillM:fillAllVDDctr;1{lay}|fillAllV@0||72|-72|||D5G4;
+IfillM:fillAllVDDctr;1{lay}|fillAllV@1||72|72|||D5G4;
+Ametal-3|net@0|||S900|fillAllG@0|gnd_9|-72|0|fillAllG@1|gnd_8|-72|0
+Ametal-3|net@1|||S900|fillAllV@0|vdd_8|72|0|fillAllV@1|vdd_13|72|0
+Ametal-8|net@17|||S0|fillAllV@0|gnd_4|0|-54|fillAllG@1|gnd_5|0|-54
+Ametal-8|net@18|||S0|fillAllV@0|gnd_6|0|-90|fillAllG@1|gnd_7|0|-90
+Ametal-8|net@19|||S0|fillAllV@0|vdd_4|0|-18|fillAllG@1|vdd_5|0|-18
+Ametal-8|net@20|||S0|fillAllV@0|vdd_6|0|-126|fillAllG@1|vdd_7|0|-126
+Ametal-8|net@21|||S0|fillAllV@1|vdd_4|0|126|fillAllG@0|vdd_5|0|126
+Ametal-8|net@22|||S0|fillAllV@1|vdd_6|0|18|fillAllG@0|vdd_7|0|18
+Ametal-8|net@23|||S0|fillAllV@1|gnd_4|0|90|fillAllG@0|gnd_5|0|90
+Ametal-8|net@24|||S0|fillAllG@0|gnd_7|0|54|fillAllV@1|gnd_6|0|54
+Ametal-9|net@26|||S900|fillAllV@0|gnd|54|0|fillAllV@1|gnd_1|54|0
+Ametal-9|net@27|||S900|fillAllV@0|gnd_2|90|0|fillAllV@1|gnd_3|90|0
+Ametal-9|net@28|||S900|fillAllV@0|vdd|18|0|fillAllV@1|vdd_1|18|0
+Ametal-9|net@29|||S900|fillAllV@0|vdd_2|126|0|fillAllV@1|vdd_3|126|0
+Ametal-9|net@30|||S900|fillAllG@0|gnd_1|-90|0|fillAllG@1|gnd|-90|0
+Ametal-9|net@31|||S900|fillAllG@0|vdd_1|-126|0|fillAllG@1|vdd|-126|0
+Ametal-9|net@32|||S900|fillAllG@0|vdd_3|-18|0|fillAllG@1|vdd_2|-18|0
+Ametal-9|net@33|||S900|fillAllG@0|gnd_3|-54|0|fillAllG@1|gnd_2|-54|0
+Egnd||D5G2;|fillAllG@0|gnd_8|G
+Egnd_1||D5G2;|fillAllG@1|gnd_9|G
+Egnd_2||D5G2;|fillAllG@0|gnd|G
+Egnd_3||D5G2;|fillAllG@0|gnd_2|G
+Egnd_4||D5G2;|fillAllG@0|gnd_4|G
+Egnd_5||D5G2;|fillAllV@0|gnd_5|G
+Egnd_6||D5G2;|fillAllG@0|gnd_6|G
+Egnd_7||D5G2;|fillAllG@1|gnd_1|G
+Egnd_8||D5G2;|fillAllG@1|gnd_3|G
+Egnd_9||D5G2;|fillAllG@1|gnd_4|G
+Egnd_10||D5G2;|fillAllG@1|gnd_6|G
+Egnd_11||D5G2;|fillAllV@0|gnd_1|G
+Egnd_12||D5G2;|fillAllV@0|gnd_3|G
+Egnd_13||D5G2;|fillAllV@0|gnd_7|G
+Egnd_14||D5G2;|fillAllV@1|gnd|G
+Egnd_15||D5G2;|fillAllV@1|gnd_2|G
+Egnd_16||D5G2;|fillAllV@1|gnd_5|G
+Egnd_17||D5G2;|fillAllV@1|gnd_7|G
+Evdd||D5G2;|fillAllV@1|vdd_8|P
+Evdd_1||D5G2;|fillAllG@1|vdd_1|P
+Evdd_2||D5G2;|fillAllG@0|vdd_2|P
+Evdd_3||D5G2;|fillAllG@1|vdd_3|P
+Evdd_4||D5G2;|fillAllG@0|vdd_4|P
+Evdd_5||D5G2;|fillAllV@0|vdd_5|P
+Evdd_6||D5G2;|fillAllG@0|vdd_6|P
+Evdd_7||D5G2;|fillAllV@0|vdd_7|P
+Evdd_11|vdd_10|D5G2;|fillAllV@0|vdd_13|P
+Evdd_11@173018779|vdd_11|D5G2;|fillAllG@0|vdd|P
+Evdd_12||D5G2;|fillAllG@1|vdd_4|P
+Evdd_13||D5G2;|fillAllG@1|vdd_6|P
+Evdd_14||D5G2;|fillAllV@0|vdd_1|P
+Evdd_15||D5G2;|fillAllV@0|vdd_3|P
+Evdd_16||D5G2;|fillAllV@1|vdd|P
+Evdd_17||D5G2;|fillAllV@1|vdd_2|P
+Evdd_18||D5G2;|fillAllV@1|vdd_5|P
+Evdd_19||D5G2;|fillAllV@1|vdd_7|P
+X