migrate jelib->delib

[fleet.git] / chips / marina / electric / driversM.delib / pred10wMC.lay

diff --git a/chips/marina/electric/driversM.delib/pred10wMC.lay b/chips/marina/electric/driversM.delib/pred10wMC.lay
new file mode 100644 (file)
index 0000000..007cda7
--- /dev/null
+++ b/chips/marina/electric/driversM.delib/pred10wMC.lay
@@ -0,0 +1,118 @@
+HdriversM|8.10k
+
+# External Libraries:
+
+LwiresL|wiresL
+
+# Cell pred10wMC;2{lay}
+Cpred10wMC;2{lay}||cmos90|1228304833003|1240848417057||ATTR_NCC(D5G3;NTY70;)S["exportsConnectedByParent vdd /vdd_[0-9]+/"]
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NMetal-1-P-Active-Con|contact@0||7.5|44||5.2||
+NMetal-1-N-Active-Con|contact@1||3.5|0||20.8||
+NMetal-1-P-Active-Con|contact@2||-12.5|44||5.2||
+NMetal-1-N-Active-Con|contact@3||-4.5|0||20.8||
+NMetal-1-N-Active-Con|contact@4||-12.5|0||20.8||
+NMetal-1-P-Active-Con|contact@5||12.5|-44||5.2||
+NMetal-1-N-Active-Con|contact@6||12.5|-9||5.2||
+NMetal-1-Polysilicon-Con|contact@10||8|54||5.2|R|
+NX-Metal-1-Metal-2-Con|contact@14||-12.5|0||6.2||
+NX-Metal-1-Metal-2-Con|contact@15||3.5|0||6.2||
+NX-Metal-1-Metal-2-Con|contact@18||-12.5|50||6.2||
+NMetal-1-P-Active-Con|contact@19||4.5|-44||5.2||
+NMetal-1-Polysilicon-Con|contact@20||7|-28||5.2||
+NMetal-1-Polysilicon-Con|contact@21||-12.5|-22.5||5.2||
+NMetal-1-Polysilicon-Con|contact@24||1.5|25||5.2||
+NX-Metal-1-Metal-2-Con|contact@25||4.5|-50||6.2||
+NN-Transistor|nmos@0||-0.5|0||26||
+NN-Transistor|nmos@1||-8.5|0||26||
+NN-Transistor|nmos@3||8.5|-9||8||
+NMetal-1-Pin|pin@28||-12.5|-21||||
+NMetal-1-Pin|pin@30||1|29.5||||
+NPolysilicon-Pin|pin@32||8.5|-30.6||||
+NMetal-1-Pin|pin@33||-4.5|-25.4||||
+NPolysilicon-Pin|pin@34||-12.5|-18||||
+NMetal-1-Pin|pin@37||13|54||||
+NPolysilicon-Pin|pin@38||-0.5|27.4||||
+NPolysilicon-Pin|pin@39||3.5|27.6||||
+NMetal-1-Pin|pin@40||13|-6.4||||
+NMetal-1-Pin|pin@43||7.5|16.5||||
+NMetal-1-Pin|pin@44||-4.5|13||||
+NMetal-1-Pin|pin@45||1|27.6||||
+NMetal-1-Pin|pin@46||-4.5|16.5||||
+NPolysilicon-Pin|pin@47||-2.5|30||||
+NPolysilicon-Pin|pin@48||-0.5|30||||
+NPolysilicon-Pin|pin@49||3.5|54||||
+IwiresL:pinsVddGnd;1{lay}|pinsVddG@0||-17|0|||D5G4;
+IwiresL:pinsVddGnd;1{lay}|pinsVddG@1||17|0|||D5G4;
+NP-Well-Node|plnode@0||0|0|39|48||A
+NN-Well-Node|plnode@1||0|-50|39|52||A
+NN-Well-Node|plnode@2||0|50|39|52||A
+NP-Select-Node|plnode@3||0|-50|36|52||A
+NP-Select-Node|plnode@4||0|50|36|52||A
+NN-Select-Node|plnode@5||0|0|36|48||A
+NP-Select-Node|plnode@6||-16.5|-31|14|14||A
+NN-Select-Node|plnode@7||-16.5|-17|14|14||A
+NP-Transistor|pmos@0||3.5|44||8||
+NP-Transistor|pmos@1||-2.5|44||8||
+NP-Transistor|pmos@2||-8.5|44||8||
+NP-Transistor|pmos@4||8.5|-44||8||
+AN-Active|net@0|||RS0|contact@1||3.5|0|nmos@0|diff-right|2.3|0
+AN-Active|net@1|||RS1800|contact@3||-4.5|0|nmos@0|diff-left|-3.3|0
+AN-Active|net@2|||RS0|contact@3||-4.5|0|nmos@1|diff-right|-5.7|0
+AN-Active|net@3|||RS1800|contact@4||-12.5|0|nmos@1|diff-left|-11.3|0
+AN-Active|net@5|||RS0|contact@6||12.5|-9|nmos@3|diff-right|11.3|-9
+AP-Active|net@6|||RS0|contact@0||7.5|44|pmos@0|diff-right|6.3|44
+AP-Active|net@7|||RS1800|contact@2||-12.5|44|pmos@2|diff-left|-11.3|44
+AP-Active|net@10|||RS1800|pmos@2|diff-right|-5.7|44|pmos@1|diff-left|-5.3|44
+AP-Active|net@11|||RS1800|pmos@1|diff-right|0.3|44|pmos@0|diff-left|0.7|44
+Ametal-2|net@62||6.2|S0|pinsVddG@1|gnd|17|0|contact@15||3.5|0
+Ametal-2|net@63||6.2|S0|contact@25||4.5|-50|pinsVddG@0|vdd_1|-17|-50
+Ametal-2|net@66||6.2|S0|contact@14||-12.5|0|pinsVddG@0|gnd|-17|0
+Ametal-1|net@67|||S0|contact@4||-12.5|0|contact@14||-12.5|0
+Ametal-2|net@68||6.2|S0|contact@15||3.5|0|contact@14||-12.5|0
+Ametal-1|net@69|||S0|contact@1||3.5|0|contact@15||3.5|0
+Ametal-1|net@87|||S2700|contact@5||12.5|-45.2|contact@6||12.5|-8
+Ametal-2|net@92||6.2|S1800|contact@18||-12.5|50|pinsVddG@1|vdd|17|50
+Ametal-2|net@93||6.2|S1800|pinsVddG@0|vdd|-17|50|contact@18||-12.5|50
+Ametal-1|net@94|||S2700|contact@2||-12.5|46.6|contact@18||-12.5|50
+AN-Active|net@95|||RS1800|contact@1||3.5|-4.5|nmos@3|diff-left|5.7|-4.5
+AP-Active|net@96|||RS1800|contact@19||4.5|-44|pmos@4|diff-left|5.7|-44
+AP-Active|net@97|||RS0|contact@5||12.5|-44|pmos@4|diff-right|11.3|-44
+APolysilicon|net@98|||S900|nmos@3|poly-bottom|8.5|-18|pin@32||8.5|-30.6
+APolysilicon|net@99|||S900|pin@32||8.5|-30.6|pmos@4|poly-top|8.5|-35
+APolysilicon|net@100|||S1800|contact@20||7|-30.6|pin@32||8.5|-30.6
+Ametal-1|net@101|||S900|contact@3||-4.5|-10.4|pin@33||-4.5|-25.4
+Ametal-1|net@102|||S1800|pin@33||-4.5|-25.4|contact@20||7|-25.4
+APolysilicon|net@103|||S0|nmos@1|poly-bottom|-8.5|-18|pin@34||-12.5|-18
+APolysilicon|net@104|||S900|pin@34||-12.5|-18|contact@21||-12.5|-19.9
+Ametal-1|net@105|||S900|pin@28||-12.5|-21|contact@21||-12.5|-21
+APolysilicon|net@111|||S2700|nmos@1|poly-top|-8.5|18|pmos@2|poly-bottom|-8.5|35
+Ametal-1|net@113|||S0|pin@37||13|54|contact@10||5.6|54
+APolysilicon|net@115|||S1800|pin@38||-0.5|27.4|contact@24||1.5|27.4
+APolysilicon|net@117|||S0|pin@39||3.5|27.6|contact@24||1.5|27.6
+Ametal-2|net@118||6.2|S0|pinsVddG@1|vdd_1|17|-50|contact@25||4.5|-50
+Ametal-1|net@119|||S900|contact@19||4.5|-46.6|contact@25||4.5|-50
+Ametal-1|net@120|||S900|pin@37||13|54|pin@40||13|-6.4
+Ametal-1|net@121|||S0|pin@40||13|-6.4|contact@6||12.5|-6.4
+APolysilicon|net@125|||S2700|nmos@0|poly-top|-0.5|18|pin@38||-0.5|27.4
+Ametal-1|net@128|||S900|pin@44||-4.5|13|contact@3||-4.5|10.4
+Ametal-1|net@129|||S900|pin@30||1|29.5|pin@45||1|27.6
+Ametal-1|net@130|||S1800|pin@45||1|27.6|contact@24||1.5|27.6
+Ametal-1|net@131|||S2700|pin@44||-4.5|13|pin@46||-4.5|16.5
+Ametal-1|net@132|||S1800|pin@46||-4.5|16.5|pin@43||7.5|16.5
+Ametal-1|net@133|||S900|contact@0||7.5|41.4|pin@43||7.5|16.5
+APolysilicon|net@134|||S900|pmos@1|poly-bottom|-2.5|35|pin@47||-2.5|30
+APolysilicon|net@135|||S2700|pin@38||-0.5|27.4|pin@48||-0.5|30
+APolysilicon|net@136|||S0|pin@48||-0.5|30|pin@47||-2.5|30
+APolysilicon|net@137|||S2700|pmos@0|poly-top|3.5|53|pin@49||3.5|54
+APolysilicon|net@138|||S1800|pin@49||3.5|54|contact@10||5.4|54
+Egnd||D5G2;|pinsVddG@0|gnd|G
+Egnd_1||D5G2;|pinsVddG@1|gnd|G
+Ein[1]||D5G2;|pin@30||I
+Emc||D5G2;|pin@28||I
+Estate[1]||D5G2;|pin@44||O
+Evdd||D5G2;|pinsVddG@0|vdd|P
+Evdd_1||D5G2;|pinsVddG@0|vdd_1|P
+Evdd_2||D5G2;|pinsVddG@1|vdd|P
+Evdd_3||D5G2;|pinsVddG@1|vdd_1|P
+X