migrate jelib->delib

[fleet.git] / chips / marina / electric / driversM.delib / predDri40.lay

diff --git a/chips/marina/electric/driversM.delib/predDri40.lay b/chips/marina/electric/driversM.delib/predDri40.lay
new file mode 100644 (file)
index 0000000..7139174
--- /dev/null
+++ b/chips/marina/electric/driversM.delib/predDri40.lay
@@ -0,0 +1,71 @@
+HdriversM|8.10k
+
+# External Libraries:
+
+LwiresL|wiresL
+
+# Cell predDri40;1{lay}
+CpredDri40;1{lay}||cmos90|1240679509573|1241981698008||ATTR_NCC(D5G3;NTY70;)S["exportsConnectedByParent vdd /vdd_[0-9]+/"]|DRC_last_good_drc_bit()I10|DRC_last_good_drc_date()G1244198340525
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NMetal-1-N-Active-Con|contact@0||0|0||20.8||
+NMetal-1-N-Active-Con|contact@1||-16|0||20.8||
+NMetal-1-N-Active-Con|contact@2||-8|0||20.8||
+NMetal-1-N-Active-Con|contact@3||8|0||20.8||
+NMetal-1-N-Active-Con|contact@4||16|0||20.8||
+NX-Metal-1-Metal-2-Con|contact@5||-16|0||6.2||
+NX-Metal-1-Metal-2-Con|contact@6||0|0||6.2||
+NX-Metal-1-Metal-2-Con|contact@7||16|0||6.2||
+NMetal-1-Polysilicon-Con|contact@8||0|-20|20.8|||
+NN-Transistor|nmos@0||-4|0||26||
+NN-Transistor|nmos@2||-12|0||26||
+NN-Transistor|nmos@3||4|0||26||
+NN-Transistor|nmos@4||12|0||26||
+NMetal-1-Pin|pin@0||-8|20||||
+NMetal-1-Pin|pin@1||8|20||||
+NPolysilicon-Pin|pin@2||-12|-20||||
+NPolysilicon-Pin|pin@3||12|-20||||
+NMetal-1-Pin|pin@4||0|-19||||
+IwiresL:pinsVddGnd;1{lay}|pinsVddG@0||-20.5|0|||D5G4;
+IwiresL:pinsVddGnd;1{lay}|pinsVddG@1||20.5|0|||D5G4;
+NP-Well-Node|plnode@0||0|0|46|48||A
+NN-Well-Node|plnode@1||0|-50|46|52||A
+NN-Well-Node|plnode@2||0|50|46|52||A
+NP-Select-Node|plnode@3||0|-50|43|52||A
+NP-Select-Node|plnode@4||0|50|43|52||A
+NN-Select-Node|plnode@5||0|0|43|48||A
+AN-Active|net@0|||RS0|contact@0||0|0|nmos@0|diff-right|-1.2|0
+AN-Active|net@1|||RS1800|contact@2||-8|0|nmos@0|diff-left|-6.8|0
+AN-Active|net@2|||RS1800|contact@1||-16|0|nmos@2|diff-left|-14.8|0
+AN-Active|net@3|||RS0|contact@2||-8|0|nmos@2|diff-right|-9.2|0
+AN-Active|net@4|||RS1800|contact@0||0|0|nmos@3|diff-left|1.2|0
+AN-Active|net@5|||RS0|contact@3||8|0|nmos@3|diff-right|6.8|0
+AN-Active|net@6|||RS1800|contact@3||8|0|nmos@4|diff-left|9.2|0
+AN-Active|net@7|||RS0|contact@4||16|0|nmos@4|diff-right|14.8|0
+Ametal-2|net@8||6.2|S1800|contact@7||16|0|pinsVddG@1|gnd|20.5|0
+Ametal-2|net@9||6.2|S0|pinsVddG@1|vdd|20.5|50|pinsVddG@0|vdd|-20.5|50
+Ametal-2|net@10||6.2|S0|pinsVddG@1|vdd_1|20.5|-50|pinsVddG@0|vdd_1|-20.5|-50
+Ametal-2|net@11||6.2|S1800|pinsVddG@0|gnd|-20.5|0|contact@5||-16|0
+Ametal-1|net@12|||S0|contact@1||-16|0|contact@5||-16|0
+Ametal-2|net@13||6.2|S1800|contact@5||-16|0|contact@6||0|0
+Ametal-1|net@14|||S0|contact@0||0|0|contact@6||0|0
+Ametal-2|net@15||6.2|S1800|contact@6||0|0|contact@7||16|0
+Ametal-1|net@16|||S0|contact@4||16|0|contact@7||16|0
+Ametal-1|net@17|||S2700|contact@2||-8|0|pin@0||-8|20
+Ametal-1|net@18|||S1800|pin@0||-8|20|pin@1||8|20
+Ametal-1|net@19|||S900|pin@1||8|20|contact@3||8|10.4
+APolysilicon|net@20|||S900|nmos@2|poly-bottom|-12|-18|pin@2||-12|-20
+APolysilicon|net@21|||S1800|pin@2||-12|-20|contact@8||-10.4|-20
+APolysilicon|net@22|||S900|nmos@0|poly-bottom|-4|-18|contact@8||-4|-20
+APolysilicon|net@23|||S900|nmos@3|poly-bottom|4|-18|contact@8||4|-20
+APolysilicon|net@24|||S900|nmos@4|poly-bottom|12|-18|pin@3||12|-20
+APolysilicon|net@25|||S0|pin@3||12|-20|contact@8||10.4|-20
+Ametal-1|net@26|||S2700|contact@8||0|-20|pin@4||0|-19
+Egnd||D5G2;|pinsVddG@0|gnd|G
+Egnd_1||D5G2;|pinsVddG@1|gnd|G
+Ein||D5G2;|pin@4||I
+Epred||D5G2;|pin@1||O
+Evdd||D5G2;|pinsVddG@0|vdd|P
+Evdd_1||D5G2;|pinsVddG@0|vdd_1|P
+Evdd_2||D5G2;|pinsVddG@1|vdd|P
+Evdd_3||D5G2;|pinsVddG@1|vdd_1|P
+X