migrate jelib->delib

[fleet.git] / chips / marina / electric / fillM.delib / fill1to8VDDctr.lay

diff --git a/chips/marina/electric/fillM.delib/fill1to8VDDctr.lay b/chips/marina/electric/fillM.delib/fill1to8VDDctr.lay
new file mode 100644 (file)
index 0000000..15365f8
--- /dev/null
+++ b/chips/marina/electric/fillM.delib/fill1to8VDDctr.lay
@@ -0,0 +1,37 @@
+HfillM|8.10k
+
+# Cell fill1to8VDDctr;1{lay}
+Cfill1to8VDDctr;1{lay}||cmos90|1238155627862|1244843148038||DRC_last_good_drc_bit()I10|DRC_last_good_drc_date()G1244843464912
+Ngeneric:Facet-Center|art@0||0|0||||AV
+Ifill4to8;1{lay}|fill4to8@0||0|0|||D5G4;
+Ifill234VDDctr;2{lay}|fill234V@1||0|0|||D5G4;
+IfillCap;2{lay}|fillCap@1||0|0|||D5G4;
+Ametal-4|net@0|||S0|fill234V@1|vdd_4|-72|36|fill4to8@0|vdd_8|-72|36
+Ametal-4|net@1|||S0|fill234V@1|gnd_3|-72|-36|fill4to8@0|gnd_8|-72|-36
+Ametal-4|net@2|||S0|fill234V@1|gnd_1|72|-36|fill4to8@0|gnd_9|72|-36
+Ametal-4|net@3|||S0|fill234V@1|vdd_1|72|36|fill4to8@0|vdd_9|72|36
+Ametal-2|net@5|||S0|fillCap@1|gnd_1|72|0|fill234V@1|gnd|72|0
+Ametal-2|net@6|||S0|fillCap@1|gnd|-72|0|fill234V@1|gnd_2|-72|0
+Ametal-2|net@7|||S0|fillCap@1|vdd_2|72|-50|fill234V@1|vdd_2|72|-50
+Ametal-2|net@8|||S0|fillCap@1|vdd|-72|-50|fill234V@1|vdd_5|-72|-50
+Ametal-2|net@9|||S0|fillCap@1|vdd_3|72|50|fill234V@1|vdd_6|72|50
+Ametal-2|net@10|||S0|fill234V@1|vdd_3|-72|50|fillCap@1|vdd_1|-72|50
+Egnd||D5G2;|fill4to8@0|gnd|U
+Egnd_2||D5G2;|fill4to8@0|gnd_10|U
+Egnd_4||D5G2;|fill4to8@0|gnd_4|G
+Egnd_5||D5G2;|fill4to8@0|gnd_5|G
+Egnd_6||D5G2;|fill4to8@0|gnd_6|G
+Egnd_7||D5G2;|fill4to8@0|gnd_7|G
+Egnd_11||D5G2;|fill4to8@0|gnd_11|U
+Egnd_12||D5G2;|fill4to8@0|gnd_12|U
+Evdd||D5G2;|fill4to8@0|vdd|U
+Evdd_2||D5G2;|fill4to8@0|vdd_10|U
+Evdd_4||D5G2;|fill4to8@0|vdd_4|P
+Evdd_5||D5G2;|fill4to8@0|vdd_5|P
+Evdd_6||D5G2;|fill4to8@0|vdd_6|P
+Evdd_7||D5G2;|fill4to8@0|vdd_7|P
+Evdd_8||D5G2;|fill234V@1|vdd|P
+Evdd_9||D5G2;|fill234V@1|vdd_7|P
+Evdd_11||D5G2;|fill4to8@0|vdd_11|U
+Evdd_12||D5G2;|fill4to8@0|vdd_12|U
+X