migrate jelib->delib

[fleet.git] / chips / marina / electric / fillM.delib / fill2to4VDDctrNar.lay

diff --git a/chips/marina/electric/fillM.delib/fill2to4VDDctrNar.lay b/chips/marina/electric/fillM.delib/fill2to4VDDctrNar.lay
new file mode 100644 (file)
index 0000000..cafe55d
--- /dev/null
+++ b/chips/marina/electric/fillM.delib/fill2to4VDDctrNar.lay
@@ -0,0 +1,45 @@
+HfillM|8.10k
+
+# Cell fill2to4VDDctrNar;1{lay}
+Cfill2to4VDDctrNar;1{lay}||cmos90|1238254564395|1241981698008||DRC_last_good_drc_bit()I10|DRC_last_good_drc_date()G1241981826991
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NX-Metal-2-Metal-3-Con|contact@2||0|50|6.2|6.2||
+NX-Metal-3-Metal-4-Con|contact@3||0|36|6.2|6.2||
+NX-Metal-2-Metal-3-Con|contact@4||0|-50|6.2|6.2||
+NMetal-2-Pin|pin@0||-72|0||||
+NMetal-2-Pin|pin@1||72|0||||
+NMetal-2-Pin|pin@2||-72|-50||||
+NMetal-2-Pin|pin@3||72|-50||||
+NMetal-2-Pin|pin@4||-72|50||||
+NMetal-2-Pin|pin@5||72|50||||
+NMetal-3-Pin|pin@6||0|72||||
+NMetal-3-Pin|pin@7||0|-72||||
+NMetal-4-Pin|pin@8||-72|-36||||
+NMetal-4-Pin|pin@9||72|-36||||
+NMetal-4-Pin|pin@10||-72|36||||
+NMetal-4-Pin|pin@11||72|36||||
+Ametal-2|net@1||6.2|IJS1800|contact@4||0|-50|pin@3||72|-50
+Ametal-2|net@2||6.2|IJS1800|contact@2||0|50|pin@5||72|50
+Ametal-4|net@9||12.2|IJS1800|contact@3||0|36|pin@11||72|36
+Ametal-4|net@11||12.2|IJS0|pin@9||72|-36|pin@8||-72|-36
+Ametal-2|net@12||6.2|IJS0|pin@1||72|0|pin@0||-72|0
+Ametal-3|net@13||9.2|IJS900|contact@3||0|36|contact@4||0|-50
+Ametal-2|net@14||6.2|IJS1800|pin@4||-72|50|contact@2||0|50
+Ametal-3|net@15||9.2|IJS900|pin@6||0|72|contact@2||0|50
+Ametal-4|net@16||12.2|IJS1800|pin@10||-72|36|contact@3||0|36
+Ametal-3|net@17||9.2|IJS900|contact@2||0|50|contact@3||0|36
+Ametal-3|net@18||9.2|IJS900|contact@4||0|-50|pin@7||0|-72
+Ametal-2|net@19||6.2|IJS1800|pin@2||-72|-50|contact@4||0|-50
+Egnd||D5G2;|pin@0||G
+Egnd_1||D5G2;|pin@1||G
+Egnd_4||D5G2;|pin@8||G
+Egnd_5||D5G2;|pin@9||G
+Evdd||D5G2;|pin@4||P
+Evdd_1||D5G2;|pin@5||P
+Evdd_2||D5G2;|pin@10||P
+Evdd_3||D5G2;|pin@11||P
+Evdd_4||D5G2;|pin@2||P
+Evdd_5||D5G2;|pin@3||P
+Evdd_6||D5G2;|pin@6||P
+Evdd_7||D5G2;|pin@7||P
+X