migrate jelib->delib

[fleet.git] / chips / marina / electric / gaspM.delib / aStage.ic

diff --git a/chips/marina/electric/gaspM.delib/aStage.ic b/chips/marina/electric/gaspM.delib/aStage.ic
new file mode 100644 (file)
index 0000000..62acb2e
--- /dev/null
+++ b/chips/marina/electric/gaspM.delib/aStage.ic
@@ -0,0 +1,52 @@
+HgaspM|8.10k
+
+# Cell aStage;1{ic}
+CaStage;1{ic}||artwork|1212797961666|1219796138042|EI
+Ngeneric:Facet-Center|art@0||0|0||||AV
+Nschematic:Bus_Pin|pin@1||0|-4|-1|-1||
+Nschematic:Bus_Pin|pin@3||-3|0|-1|-1||
+Nschematic:Bus_Pin|pin@4||-1|4|-1|-1||
+Nschematic:Bus_Pin|pin@5||1|4|-1|-1||
+Nschematic:Bus_Pin|pin@6||3|0|-1|-1||
+NPin|pin@12||-2|3|1|1||
+NPin|pin@13||2|3|1|1||
+Ngeneric:Invisible-Pin|pin@19||0|0|||||ART_message(D5G2;)S[a,stg]
+NPin|pin@25||-2|-3|1|1||
+NPin|pin@26||2|-3|1|1||
+NPin|pin@34||-1|3|1|1||
+NPin|pin@35||-1|4|1|1||
+NPin|pin@41||1|3|1|1||
+NPin|pin@42||1|4|1|1||
+NPin|pin@43||-1|2|1|1||
+NPin|pin@44||1|2|1|1||
+NPin|pin@45||0.5|2.5|1|1||
+NPin|pin@46||0.5|1.5|1|1||
+NPin|pin@56||-2|0|1|1||
+NPin|pin@57||-3|0|1|1||
+NPin|pin@60||0|-3|1|1||
+NPin|pin@61||0|-4|1|1||
+NPin|pin@62||2|0|1|1||
+NPin|pin@63||3|0|1|1||
+AThicker|net@24|||FS1800|pin@34||-1|3|pin@41||1|3
+AThicker|net@25|||FS1800|pin@12||-2|3|pin@34||-1|3
+AThicker|net@26|||FS2700|pin@34||-1|3|pin@35||-1|4
+AThicker|net@34|||FS1800|pin@41||1|3|pin@13||2|3
+AThicker|net@35|||FS2700|pin@41||1|3|pin@42||1|4
+AThicker|net@36|||FS1800|pin@43||-1|2|pin@44||1|2
+AThicker|net@37|||FS3150|pin@44||1|2|pin@45||0.5|2.5
+AThicker|net@38|||FS450|pin@44||1|2|pin@46||0.5|1.5
+AThicker|net@43|||FS2700|pin@25||-2|-3|pin@56||-2|0
+AThicker|net@48|||FS1800|pin@60||0|-3|pin@26||2|-3
+AThicker|net@50|||FS0|pin@56||-2|0|pin@57||-3|0
+AThicker|net@52|||FS1800|pin@25||-2|-3|pin@60||0|-3
+AThicker|net@53|||FS900|pin@60||0|-3|pin@61||0|-4
+AThicker|net@54|||FS2700|pin@62||2|0|pin@13||2|3
+AThicker|net@55|||FS2700|pin@26||2|-3|pin@62||2|0
+AThicker|net@56|||FS1800|pin@62||2|0|pin@63||3|0
+AThicker|net@57|||FS900|pin@12||-2|3|pin@56||-2|0
+Efire||D5G2;|pin@1||O
+Emc||D5G2;|pin@4||I
+Epred||D5G2;|pin@3||I
+Es[1]||D5G2;|pin@5||O
+Esucc||D5G2;|pin@6||O
+X