migrate jelib->delib

[fleet.git] / chips / marina / electric / jtagController.delib / stateBit.sch

diff --git a/chips/marina/electric/jtagController.delib/stateBit.sch b/chips/marina/electric/jtagController.delib/stateBit.sch
new file mode 100644 (file)
index 0000000..29606da
--- /dev/null
+++ b/chips/marina/electric/jtagController.delib/stateBit.sch
@@ -0,0 +1,66 @@
+HjtagController|8.10k
+
+# External Libraries:
+
+LjtagScan|jtagScan
+
+LorangeTSMC090nm|orangeTSMC090nm
+
+LredFive|redFive
+
+# Cell stateBit;2{sch}
+CstateBit;2{sch}||schematic|1031347345000|1187021081456|I
+NOff-Page|conn@0||-23|9|||RRR|
+NOff-Page|conn@1||4|9|||RRR|
+NOff-Page|conn@2||19.5|-33|||RRR|
+NOff-Page|conn@3||-3|-24.5|||RRR|
+NOff-Page|conn@4||-42|0||||
+NOff-Page|conn@5||27|-29.5|||RRR|
+NOff-Page|conn@6||-9.5|4|||XY|
+NGround|gnd@1||-18|10.5|||RR|
+IredFive:inv;1{ic}|inv@0||19.5|-17|RRR||D0G4;|ATTR_Delay(D5G1;NPX2;Y-2;)I100|ATTR_X(D5G1.5;NPX1.5;Y2;)F3.3|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1
+IredFive:inv;1{ic}|inv@1||19.5|-7|RRR||D0G4;|ATTR_Delay(D5G1;NPX2;Y-2;)I100|ATTR_X(D5G1.5;NPX1.5;Y2;)F3.3|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1
+IredFive:inv;1{ic}|inv@2||-3|-8|RRR||D0G4;|ATTR_Delay(D5G1;NPX2;Y-2;)I100|ATTR_X(D5G1.5;NPX1.5;Y2;)F6.6|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1
+NWire_Pin|pin@2||-3|0||||
+NWire_Pin|pin@3||19.5|0||||
+Ngeneric:Invisible-Pin|pin@4||-8|19.5|||||ART_message(D5G5;)S[stateBit]
+Ngeneric:Invisible-Pin|pin@5||-10|16|||||ART_message(D5G2;)S[master/slave state-holding bit]
+NWire_Pin|pin@6||27|-12||||
+NWire_Pin|pin@7||19.5|-12||||
+NWire_Pin|pin@15||-42.25|0||||
+IjtagScan:scan_write;1{ic}|scan_wri@0||7|0|||D5G4;
+IjtagScan:scan_write_mc;1{ic}|scan_wri@1||-18|0|||D5G4;
+IstateBit;1{ic}|stateBit@0||18|11|||D0G4;
+IorangeTSMC090nm:wire90;1{ic}|wire180@0||-3|-16.75|RRR||D0G4;|ATTR_L(D5G1;PUD)I750|ATTR_LEWIRE(P)I1|ATTR_layer(D5G1;NPY-1;)I1|ATTR_width(D5G1;NPY-2;)I3
+IorangeTSMC090nm:wire90;1{ic}|wire180@1||19.5|-24.75|RRR||D0G4;|ATTR_L(D5G1;PUD)I1000|ATTR_LEWIRE(P)I1|ATTR_layer(D5G1;NPY-1;)I1|ATTR_width(D5G1;NPY-2;)I3
+IorangeTSMC090nm:wire90;1{ic}|wire180@2||27|-19.25|RRR||D0G4;|ATTR_L(D5G1;PUD)I500|ATTR_LEWIRE(P)I1|ATTR_layer(D5G1;NPY-1;)I1|ATTR_width(D5G1;NPY-2;)I3
+IorangeTSMC090nm:wire90;1{ic}|wire180@3||-34|0|||D0G4;|ATTR_L(D5G1;PUD)I100|ATTR_LEWIRE(P)I1|ATTR_layer(D5G1;NPY-1;)I1|ATTR_width(D5G1;NPY-2;)I3
+Awire|net@21|||900|pin@7||19.5|-12|inv@0|in|19.5|-14.5
+Awire|net@22|||2700|inv@1|in|19.5|-4.5|pin@3||19.5|0
+Awire|net@23|||900|inv@1|out|19.5|-9.5|pin@7||19.5|-12
+Awire|net@24|||900|pin@2||-3|0|inv@2|in|-3|-5.5
+Awire|net@25|||1800|pin@7||19.5|-12|pin@6||27|-12
+Awire|net@26|||1800|scan_wri@0|dout|13|0|pin@3||19.5|0
+Awire|net@27|||0|scan_wri@0|din|2|0|pin@2||-3|0
+Awire|net@28|||900|conn@1|y|4|7|scan_wri@0|wr|4|2
+Awire|net@30|||1800|scan_wri@1|dout|-10|0|pin@2||-3|0
+Awire|net@31|||900|conn@0|y|-23|7|scan_wri@1|wr|-23|2
+Awire|net@33|||900|gnd@1||-18|8.5|scan_wri@1|mcdata|-18|6
+Awire|net@34|||0|conn@6|y|-11.5|4|scan_wri@1|mc|-16|4
+Awire|net@44|||0|wire180@3|a|-36.5|0|pin@15||-42.25|0
+Awire|net@62|||1800|pin@15||-42.25|0|conn@4|y|-40|0
+Awire|net@67|||900|wire180@2|b|27|-21.75|conn@5|a|27|-27.5
+Awire|net@68|||2700|conn@3|a|-3|-22.5|wire180@0|b|-3|-19.25
+Awire|net@71|||2700|conn@2|a|19.5|-31|wire180@1|b|19.5|-27.25
+Awire|net@72|||900|inv@0|out|19.5|-19.5|wire180@1|a|19.5|-22.25
+Awire|net@73|||2700|wire180@2|a|27|-16.75|pin@6||27|-12
+Awire|net@74|||0|scan_wri@1|wrdata|-25|0|wire180@3|b|-31.5|0
+Awire|net@75|||900|inv@2|out|-3|-10.5|wire180@0|a|-3|-14.25
+Emaster||D5G2;|conn@3|y|O
+Enext||D5G2;|conn@4|y|I
+Ephi1||D5G2;|conn@0|y|I
+Ephi2||D5G2;|conn@1|y|I
+Erst||D5G2;|conn@6|y|I
+Eslave||D5G2;|conn@2|y|O
+EslaveBar||D5G2;|conn@5|y|O
+X