migrate jelib->delib

[fleet.git] / chips / marina / electric / jtagController.delib / stateBitHI.sch

diff --git a/chips/marina/electric/jtagController.delib/stateBitHI.sch b/chips/marina/electric/jtagController.delib/stateBitHI.sch
new file mode 100644 (file)
index 0000000..9d12045
--- /dev/null
+++ b/chips/marina/electric/jtagController.delib/stateBitHI.sch
@@ -0,0 +1,68 @@
+HjtagController|8.10k
+
+# External Libraries:
+
+LjtagScan|jtagScan
+
+LorangeTSMC090nm|orangeTSMC090nm
+
+LredFive|redFive
+
+# Cell stateBitHI;2{sch}
+CstateBitHI;2{sch}||schematic|1031347345000|1187020197827|I
+NOff-Page|conn@0||-7|4|||X|
+NOff-Page|conn@1||27|-27.5|||RRR|
+NOff-Page|conn@2||-43.5|0||||
+NOff-Page|conn@3||-4|-24|||RRR|
+NOff-Page|conn@4||19.5|-31|||RRR|
+NOff-Page|conn@5||3|9|||RRR|
+NOff-Page|conn@6||-22|9|||RRR|
+IredFive:inv;1{ic}|inv@0||19.5|-17|RRR||D0G4;|ATTR_Delay(D5G1;NPX2;Y-2;)I100|ATTR_X(D5G1.5;NPX1.5;Y2;)F3.3|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1
+IredFive:inv;1{ic}|inv@1||19.5|-7|RRR||D0G4;|ATTR_Delay(D5G1;NPX2;Y-2;)I100|ATTR_X(D5G1.5;NPX1.5;Y2;)F3.3|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1
+IredFive:inv;1{ic}|inv@2||-4|-8|RRR||D0G4;|ATTR_Delay(D5G1;NPX2;Y-2;)I100|ATTR_X(D5G1.5;NPX1.5;Y2;)F6.6|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1
+NWire_Pin|pin@0||19.5|-12||||
+NWire_Pin|pin@1||27|-12||||
+Ngeneric:Invisible-Pin|pin@2||-5|19.5|||||ART_message(D5G2;)S[master/slave state-holding bit (reset hi)]
+Ngeneric:Invisible-Pin|pin@3||-3|23|||||ART_message(D5G5;)S[stateBitHI]
+NWire_Pin|pin@4||19.5|0||||
+NWire_Pin|pin@5||-4|0||||
+NWire_Pin|pin@11||-42.75|0||||
+NWire_Pin|pin@21||-4|-16.125||||
+NPower|pwr@0||-17|10||||
+IjtagScan:scan_write_mc;1{ic}|scan_wri@0||-17|0|||D5G4;
+IjtagScan:scan_write;1{ic}|scan_wri@1||6|0|||D5G4;
+IstateBitHI;1{ic}|stateBit@0||18|11|||D0G4;
+IorangeTSMC090nm:wire90;1{ic}|wire180@0||19.5|-23.75|RRR||D0G4;|ATTR_L(D5G1;PUD)I1000|ATTR_LEWIRE(P)I1|ATTR_layer(D5G1;NPY-1;)I1|ATTR_width(D5G1;NPY-2;)I3
+IorangeTSMC090nm:wire90;1{ic}|wire180@1||27|-17.75|RRR||D0G4;|ATTR_L(D5G1;PUD)I500|ATTR_LEWIRE(P)I1|ATTR_layer(D5G1;NPY-1;)I1|ATTR_width(D5G1;NPY-2;)I3
+IorangeTSMC090nm:wire90;1{ic}|wire180@2||-33.5|0|||D0G4;|ATTR_L(D5G1;PUD)I100|ATTR_LEWIRE(P)I1|ATTR_layer(D5G1;NPY-1;)I1|ATTR_width(D5G1;NPY-2;)I3
+IorangeTSMC090nm:wire90;1{ic}|wire180@3||-4|-15.75|RRR||D0G4;|ATTR_L(D5G1;PUD)I750|ATTR_LEWIRE(P)I1|ATTR_layer(D5G1;NPY-1;)I1|ATTR_width(D5G1;NPY-2;)I3
+Awire|net@19|||900|pin@0||19.5|-12|inv@0|in|19.5|-14.5
+Awire|net@20|||2700|inv@1|in|19.5|-4.5|pin@4||19.5|0
+Awire|net@21|||900|inv@1|out|19.5|-9.5|pin@0||19.5|-12
+Awire|net@22|||900|pin@5||-4|0|inv@2|in|-4|-5.5
+Awire|net@23|||1800|pin@0||19.5|-12|pin@1||27|-12
+Awire|net@26|||0|pin@5||-4|0|scan_wri@0|dout|-9|0
+Awire|net@30|||900|pwr@0||-17|10|scan_wri@0|mcdata|-17|6
+Awire|net@31|||0|conn@0|y|-9|4|scan_wri@0|mc|-15|4
+Awire|net@32|||900|conn@6|y|-22|7|scan_wri@0|wr|-22|2
+Awire|net@33|||0|scan_wri@1|din|1|0|pin@5||-4|0
+Awire|net@34|||1800|scan_wri@1|dout|12|0|pin@4||19.5|0
+Awire|net@35|||2700|scan_wri@1|wr|3|2|conn@5|y|3|7
+Awire|net@42|||0|wire180@2|a|-36|0|pin@11||-42.75|0
+Awire|net@57|||2700|conn@3|a|-4|-22|pin@21||-4|-16.125
+Awire|net@61|||900|pin@1||27|-12|wire180@1|a|27|-15.25
+Awire|net@63|||900|wire180@1|b|27|-20.25|conn@1|a|27|-25.5
+Awire|net@65|||900|inv@0|out|19.5|-19.5|wire180@0|a|19.5|-21.25
+Awire|net@66|||900|wire180@0|b|19.5|-26.25|conn@4|a|19.5|-29
+Awire|net@68|||1800|pin@11||-42.75|0|conn@2|y|-41.5|0
+Awire|net@70|||900|pin@21||-4|-16.125|wire180@3|b|-4|-18.25
+Awire|net@71|||1800|wire180@2|b|-31|0|scan_wri@0|wrdata|-24|0
+Awire|net@72|||900|inv@2|out|-4|-10.5|wire180@3|a|-4|-13.25
+Emaster||D5G2;|conn@3|y|O
+Enext||D5G2;|conn@2|y|I
+Ephi1||D5G2;|conn@6|y|I
+Ephi2||D5G2;|conn@5|y|I
+Erst||D5G2;|conn@0|y|I
+Eslave||D5G2;|conn@4|y|O
+EslaveBar||D5G2;|conn@1|y|O
+X