migrate jelib->delib

[fleet.git] / chips / marina / electric / jtagController.delib / tsinvBig.sch

diff --git a/chips/marina/electric/jtagController.delib/tsinvBig.sch b/chips/marina/electric/jtagController.delib/tsinvBig.sch
new file mode 100644 (file)
index 0000000..b929588
--- /dev/null
+++ b/chips/marina/electric/jtagController.delib/tsinvBig.sch
@@ -0,0 +1,61 @@
+HjtagController|8.10k
+
+# External Libraries:
+
+LredFive|redFive
+
+# Cell tsinvBig;1{sch}
+CtsinvBig;1{sch}||schematic|1028844462000|1185367908213|I|FACET_schematic_page_size()Sa|USER_drawing_designer_name()Sivans|prototype_center()I[0,0]
+IredFive:NMOS;1{ic}|NMOS@0||10|-13|||D0G4;|ATTR_Delay(D5G1;NPX3.5;Y-2;)I100|ATTR_X(D5G1.5;NPX3.5;Y0.5;)I8
+IredFive:NMOS;1{ic}|NMOS@1||10|-6|YRR||D0G4;|ATTR_Delay(D5G1;NPX3.5;Y-2;)I100|ATTR_X(D5G1.5;NPX3.5;Y0.5;)I8
+IredFive:NMOS;1{ic}|NMOS@2||0|-6|YRR||D0G4;|ATTR_Delay(D5G1;NPX3.5;Y-2;)I100|ATTR_X(D5G1.5;NPX3.5;Y0.5;)I8
+IredFive:NMOS;1{ic}|NMOS@3||0|-13|||D0G4;|ATTR_Delay(D5G1;NPX3.5;Y-2;)I100|ATTR_X(D5G1.5;NPX3.5;Y0.5;)I8
+IredFive:PMOS;1{ic}|PMOS@0||10|6|YRR||D0G4;|ATTR_Delay(D5G1;NPX3.5;Y-2;)I100|ATTR_X(D5G1.5;NPX3.5;Y0.5;)I4
+IredFive:PMOS;1{ic}|PMOS@1||10|12.5|||D0G4;|ATTR_Delay(D5G1;NPX3.5;Y-2;)I100|ATTR_X(D5G1.5;NPX3.5;Y0.5;)I4
+IredFive:PMOS;1{ic}|PMOS@2||0|6|YRR||D0G4;|ATTR_Delay(D5G1;NPX3.5;Y-2;)I100|ATTR_X(D5G1.5;NPX3.5;Y0.5;)I4
+IredFive:PMOS;1{ic}|PMOS@3||0|12.5|||D0G4;|ATTR_Delay(D5G1;NPX3.5;Y-2;)I100|ATTR_X(D5G1.5;NPX3.5;Y0.5;)I4
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NOff-Page|conn@0||20|6|||YRR|
+NOff-Page|conn@1||-11|0||||
+NOff-Page|conn@2||20|-6|||YRR|
+NOff-Page|conn@3||20|0||||
+NGround|gnd@0||10|-20.5||||
+NGround|gnd@1||0|-20.5||||
+NWire_Pin|pin@0||0|0||||
+NWire_Pin|pin@1||10|0||||
+NWire_Pin|pin@2||-6|12.5||||
+NWire_Pin|pin@3||-6|-13||||
+NWire_Pin|pin@4||-6|0||||
+NPower|pwr@0||10|19||||
+NPower|pwr@1||0|19||||
+ItsinvBig;1{ic}|tsinvBig@0||37.75|30|||D0G4;
+Awire|net@0|||1800|pin@0||0|0|pin@1||10|0
+Awire|net@1|||900|PMOS@2|d|0|4|pin@0||0|0
+Awire|net@2|||900|pin@0||0|0|NMOS@2|d|0|-4
+Awire|net@3|||1800|pin@1||10|0|conn@3|a|18|0
+Awire|net@4|||2700|NMOS@1|d|10|-4|pin@1||10|0
+Awire|net@5|||2700|pin@1||10|0|PMOS@0|d|10|4
+Awire|net@6|||1800|NMOS@3|g|-3|-13|NMOS@0|g|7|-13
+Awire|net@7|||1800|NMOS@1|g|13|-6|conn@2|y|18|-6
+Awire|net@8|||0|NMOS@1|g|13|-6|NMOS@2|g|3|-6
+Awire|net@9|||1800|PMOS@0|g|13|6|conn@0|y|18|6
+Awire|net@10|||0|PMOS@0|g|13|6|PMOS@2|g|3|6
+Awire|net@11|||0|PMOS@1|g|7|12.5|PMOS@3|g|-3|12.5
+Awire|net@12|||2700|gnd@0||10|-18.5|NMOS@0|s|10|-15
+Awire|net@13|||2700|NMOS@0|d|10|-11|NMOS@1|s|10|-8|NET_ncc_match()SNCCmatch2
+Awire|net@14|||2700|PMOS@0|s|10|8|PMOS@1|d|10|10.5|NET_ncc_match()SNCCmatch4
+Awire|net@15|||2700|PMOS@1|s|10|14.5|pwr@0||10|19
+Awire|net@16|||2700|pin@4||-6|0|pin@2||-6|12.5
+Awire|net@17|||2700|pin@3||-6|-13|pin@4||-6|0
+Awire|net@18|||1800|conn@1|y|-9|0|pin@4||-6|0
+Awire|net@19|||900|pwr@1||0|19|PMOS@3|s|0|14.5
+Awire|net@20|||1800|pin@2||-6|12.5|PMOS@3|g|-3|12.5
+Awire|net@21|||1800|pin@3||-6|-13|NMOS@3|g|-3|-13
+Awire|net@22|||2700|PMOS@2|s|0|8|PMOS@3|d|0|10.5|NET_ncc_match()SNCCmatch3
+Awire|net@23|||900|NMOS@2|s|0|-8|NMOS@3|d|0|-11|NET_ncc_match()SNCCmatch1
+Awire|net@24|||2700|gnd@1||0|-18.5|NMOS@3|s|0|-15
+EDin||D5G2;|conn@1|a|I
+EDout||D5G2;|conn@3|y|O
+Een||D5G2;|conn@2|a|I
+Eenb||D5G2;|conn@0|a|I
+X