migrate jelib->delib

[fleet.git] / chips / marina / electric / jtagScan.delib / scanCH.sch

diff --git a/chips/marina/electric/jtagScan.delib/scanCH.sch b/chips/marina/electric/jtagScan.delib/scanCH.sch
new file mode 100644 (file)
index 0000000..deeddb5
--- /dev/null
+++ b/chips/marina/electric/jtagScan.delib/scanCH.sch
@@ -0,0 +1,52 @@
+HjtagScan|8.10k
+
+# Cell scanCH;1{sch}
+CscanCH;1{sch}||schematic|1071024063000|1185367908213|I|FACET_schematic_page_size()Sh|USER_drawing_designer_name()Sivans|prototype_center()I[0,0]
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NOff-Page|conn@1||12|22|||RRR|
+NOff-Page|conn@4||-34|-20.5||||
+NOff-Page|conn@5||27|-20.5||||
+Ngeneric:Invisible-Pin|pin@12||1|-17|||||ART_message(D5G2;)Sscan write is unused here
+Ngeneric:Invisible-Pin|pin@13||-0.5|32.5|||||ART_message(D5G2;)S["scanCH serves as a keeper for \"con[0]\""]
+Ngeneric:Invisible-Pin|pin@14||-2.5|36.5|||||ART_message(D5G6;)S[scanCH]
+Ngeneric:Invisible-Pin|pin@15||-0.5|29.5|||||ART_message(D5G2;)Sit sets con[0] to HI on Master Clear
+NWire_Pin|pin@21||8|-6||||
+NBus_Pin|pin@22||-15|4||||
+NBus_Pin|pin@23||-2|4||||
+NBus_Pin|pin@24||8|4||||
+NBus_Pin|pin@28||18|4||||
+NWire_Pin|pin@29||3|14||||
+NBus_Pin|pin@30||-24|-20.5|-1|-1||
+NBus_Pin|pin@31||-24|-27.5|-1|-1||
+NBus_Pin|pin@32||-11|-20.5|-1|-1||
+NBus_Pin|pin@33||-6|-20.5|-1|-1||
+NWire_Pin|pin@34||-33|-10||||
+NWire_Pin|pin@35||26|-10||||
+NBus_Pin|pin@36||-39|4||||
+NPower|pwr@0||25|14||||
+IscanCH;1{ic}|scanCH@0||43|30|||D0G4;
+Iscan_shift;1{ic}|scan_shi@0||-2|-10|||D5G4;
+Iscan_write_sizeable;1{ic}|scan_wri@0||15|14|XY||D5G4;
+Awire|mc|D5G2;||900|scan_wri@0|wr|18|12|pin@28||18|4
+Abus|net@35||-0.5|IJ1800|pin@22||-15|4|pin@23||-2|4
+Abus|net@37||-0.5|IJ1800|pin@23||-2|4|pin@24||8|4
+Awire|net@44|||2700|scan_shi@0|rddata|3|-4|pin@29||3|14
+Awire|net@47|||1800|scan_shi@0|rd|5|-6|pin@21||8|-6
+Abus|net@50||-0.5|IJ0|pin@28||18|4|pin@24||8|4
+Awire|net@53|||900|conn@1|y|12|20|scan_wri@0|kept|12|17
+Awire|net@54|||0|scan_wri@0|dout|9|14|pin@29||3|14
+Abus|net@55||-0.5|IJ1800|conn@4|y|-32|-20.5|pin@30||-24|-20.5
+Abus|net@56||-0.5|IJ1800|pin@30||-24|-20.5|pin@32||-11|-20.5
+Awire|net@57|||0|pwr@0||25|14|scan_wri@0|din|20|14
+Awire|phi1|D5G2;Y-4;||2700|scan_shi@0|phi1|-2|-8|pin@23||-2|4
+Awire|phi2|D5G2;||2700|scan_shi@0|phi2|-15|-8|pin@22||-15|4
+Abus|phi2,phi1,rd,mc|D8G2;Y0.25;|-0.5|IJ1800|pin@36||-39|4|pin@22||-15|4|ART_color()I0
+Awire|rd|D5G2;||2700|pin@21||8|-6|pin@24||8|4
+Awire|sin|D8G2;||0|scan_shi@0|sdin|-17|-10|pin@34||-33|-10|ART_color()I0
+Abus|sin,phi2,phi1,wr,rd,phi1_return,phi2_return,scan_data_return,mc|D5G2;|-0.5|IJ900|pin@30||-24|-20.5|pin@31||-24|-27.5
+Awire|sout|D8G2;||1800|scan_shi@0|sdout|12|-10|pin@35||26|-10|ART_color()I0
+Abus|sout,jtagIn[2:8],mc|D8G2;Y0.25;|-0.5|IJ0|conn@5|a|25|-20.5|pin@33||-6|-20.5
+Econ[0]||D5G2;X-1;|conn@1|a|B
+EjtagIn[8:0]|jtagIn[1:9]|D5G2;|conn@4|a|B
+EjtagOut[8:0]|jtagOut[1:9]|D5G2;|conn@5|y|B
+X