migrate jelib->delib

[fleet.git] / chips / marina / electric / jtagScan.delib / scanR.sch

diff --git a/chips/marina/electric/jtagScan.delib/scanR.sch b/chips/marina/electric/jtagScan.delib/scanR.sch
new file mode 100644 (file)
index 0000000..ea47865
--- /dev/null
+++ b/chips/marina/electric/jtagScan.delib/scanR.sch
@@ -0,0 +1,49 @@
+HjtagScan|8.10k
+
+# External Libraries:
+
+LredFive|redFive
+
+# Cell scanR;1{sch}
+CscanR;1{sch}||schematic|992379436000|1185367908213|I|FACET_schematic_page_size()Sh|USER_drawing_designer_name()Sivans|prototype_center()I[0,-32000]
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NOff-Page|conn@2||4|21|||R|
+NOff-Page|conn@5||-48|-25||||
+NOff-Page|conn@6||13|-25||||
+IredFive:inv;1{ic}|inv@0||4|10.5|YR||D0G4;|ATTR_Delay(D5G1;NPX2;Y-2;)I100|ATTR_X(D5G1.5;NPX1.5;Y2;)S3.6|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1
+Ngeneric:Invisible-Pin|pin@0||-4|-12.5|||||ART_message(D5G2;)Sscan write and master clear are unused here
+Ngeneric:Invisible-Pin|pin@5||-6.5|31.5|||||ART_message(D5G2;)S[the inverter keeps the sense of the datapath consistent]
+Ngeneric:Invisible-Pin|pin@6||-8.5|39|||||ART_message(D5G6;)SscanR
+Ngeneric:Invisible-Pin|pin@7||-6.5|33.5|||||ART_message(D5G2;)SscanR is a read-only version of the scan chain bit
+NBus_Pin|pin@8||-14|4||||
+NBus_Pin|pin@9||-1|4||||
+NWire_Pin|pin@10||10|-4||||
+NBus_Pin|pin@11||10|4||||
+NBus_Pin|pin@12||-38|-25|-1|-1||
+NBus_Pin|pin@13||-38|-32|-1|-1||
+NBus_Pin|pin@14||-25|-25|-1|-1||
+NBus_Pin|pin@15||-20|-25|-1|-1||
+NBus_Pin|pin@16||-30|4|-1|-1||
+NWire_Pin|pin@18||-26|-8||||
+NWire_Pin|pin@19||21|-8||||
+IscanR;1{ic}|scanBBro@0||33|20|||D0G4;
+Iscan_shift;1{ic}|scan_shi@0||-1|-8|||D5G4;
+Awire|net@0|||900|conn@2|a|4|19|inv@0|in|4|13
+Abus|net@11|||IJ0|pin@9||-1|4|pin@8||-14|4
+Awire|net@19|||900|inv@0|out|4|8|scan_shi@0|rddata|4|-2
+Awire|net@20|||1800|scan_shi@0|rd|6|-4|pin@10||10|-4
+Abus|net@21|||IJ0|pin@11||10|4|pin@9||-1|4
+Abus|net@22||-0.5|IJ1800|conn@5|y|-46|-25|pin@12||-38|-25
+Abus|net@23||-0.5|IJ1800|pin@12||-38|-25|pin@14||-25|-25
+Awire|phi1|D5G2;||900|pin@9||-1|4|scan_shi@0|phi1|-1|-6
+Awire|phi2|D5G2;||900|pin@8||-14|4|scan_shi@0|phi2|-14|-6
+Abus|phi2,phi1,rd|D8G2;Y0.5;||IJ0|pin@8||-14|4|pin@16||-30|4
+Awire|rd|D5G2;||2700|pin@10||10|-4|pin@11||10|4
+Awire|sin|D8G2;||0|scan_shi@0|sdin|-16|-8|pin@18||-26|-8
+Abus|sin,phi2,phi1,wr,rd,phi1_return,phi2_return,scan_data_return,mc|D5G2;|-0.5|IJ900|pin@12||-38|-25|pin@13||-38|-32
+Awire|sout|D8G2;||1800|scan_shi@0|sdout|13|-8|pin@19||21|-8
+Abus|sout,jtagIn[2:8],mc|D8G2;Y0.25;|-0.5|IJ0|conn@6|a|11|-25|pin@15||-20|-25
+Edin[0]|din|D5G2;|conn@2|y|I
+EjtagIn[8:0]|jtagIn[1:9]|D5G2;|conn@5|a|B
+EjtagOut[8:0]|jtagOut[1:9]|D5G2;|conn@6|y|B
+X