migrate jelib->delib
[fleet.git] / chips / marina / electric / latchGroupsK.delib / dataMux.lay
diff --git a/chips/marina/electric/latchGroupsK.delib/dataMux.lay b/chips/marina/electric/latchGroupsK.delib/dataMux.lay
new file mode 100644 (file)
index 0000000..952cabb
--- /dev/null
@@ -0,0 +1,50 @@
+HlatchGroupsK|8.10k
+
+# External Libraries:
+
+Lgates2inM|gates2inM
+
+LlatchesK|latchesK
+
+LwiresL|wiresL
+
+# Cell dataMux;3{lay}
+CdataMux;3{lay}||cmos90|1216073469078|1241981698008||ATTR_NCC(D5G3;NTY70;)S["exportsConnectedByParent vdd /vdd_[0-9]+/"]|DRC_last_good_drc_bit()I10|DRC_last_good_drc_date()G1241982205540
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NX-Metal-1-Metal-2-Con|contact@0||-1|28||||
+NMetal-1-Polysilicon-Con|contact@1||-35|62||5.2||
+NX-Metal-1-Metal-2-Con|contact@2||-39.5|-10||||
+NX-Metal-1-Metal-2-Con|contact@3||41.8|-16||||
+IlatchesK:latch1in09.6Bi;1{lay}|latch1in@0||-18.5|0|||D5G4;
+Igates2inM:mux5;3{lay}|mux5@1||39|0|||D5G4;
+NMetal-1-Pin|pin@2||-35|66||||
+NMetal-2-Pin|pin@3||-32|-10||||
+NMetal-2-Pin|pin@4||33|-16||||
+IwiresL:wellContacts13;1{lay}|wellCont@1||16|0|||D5G4;
+Ametal-2|net@2|||S0|wellCont@1|gnd|11.5|0|latch1in@0|gnd_1|11.5|0
+Ametal-2|net@3|||S0|wellCont@1|vdd|11.5|-50|latch1in@0|vdd_1|11.5|-50
+Ametal-2|net@4|||S0|wellCont@1|vdd_1|11.5|50|latch1in@0|vdd_3|11.5|50
+Ametal-2|net@5|||S0|wellCont@1|gnd_1|20.5|0|mux5@1|gnd_1|20.5|0
+Ametal-2|net@6|||S0|wellCont@1|vdd_2|20.5|-50|mux5@1|vdd_3|20.5|-50
+Ametal-2|net@7|||S0|wellCont@1|vdd_3|20.5|50|mux5@1|vdd_2|20.5|50
+Ametal-2|net@8|||S0|mux5@1|inA[1]|33.5|28|contact@0||-1|28
+Ametal-1|net@9|||S2700|latch1in@0|out[1]|-1|25|contact@0||-1|28
+APolysilicon|net@10|||S900|contact@1||-35|59.4|latch1in@0|hcl|-35|58.5
+Ametal-1|net@11|||S2700|contact@1||-35|62|pin@2||-35|66
+Ametal-2|net@16|||S0|pin@3||-32|-10|contact@2||-39.5|-10
+Ametal-1|net@17|||S900|latch1in@0|in[1]|-39.5|-7|contact@2||-39.5|-10
+Ametal-2|net@18|||S1800|pin@4||33|-16|contact@3||41.8|-16
+Ametal-1|net@19||0.4|S900|mux5@1|out[1]|41.8|-11|contact@3||41.8|-16
+Egnd||D5G2;|latch1in@0|gnd|G
+Egnd_1||D5G2;|mux5@1|gnd|G
+Ehcl||D5G2;|pin@2||I
+EinB[1]||D5G2;|mux5@1|inB[1]|I
+Ein[2]|in[1]|D5G2;|pin@3||I
+Eout[1]||D5G2;|pin@4||O
+Es[F]||D5G2;|mux5@1|s[F]|I
+Es[T]||D5G2;|mux5@1|s[T]|I
+Evdd||D5G2;|latch1in@0|vdd|P
+Evdd_1||D5G2;|mux5@1|vdd_1|P
+Evdd_2||D5G2;|latch1in@0|vdd_2|P
+Evdd_3||D5G2;|mux5@1|vdd|P
+X