migrate jelib->delib

[fleet.git] / chips / marina / electric / latchPartsK.delib / dataMux10.sch

diff --git a/chips/marina/electric/latchPartsK.delib/dataMux10.sch b/chips/marina/electric/latchPartsK.delib/dataMux10.sch
new file mode 100644 (file)
index 0000000..b744097
--- /dev/null
+++ b/chips/marina/electric/latchPartsK.delib/dataMux10.sch
@@ -0,0 +1,67 @@
+HlatchPartsK|8.10k
+
+# External Libraries:
+
+LorangeTSMC090nm|orangeTSMC090nm
+
+LredFive|redFive
+
+# Cell dataMux10;1{sch}
+CdataMux10;1{sch}||schematic|1204399273102|1205532853617|
+IorangeTSMC090nm:NMOSx;1{ic}|NMOSx@0||12|-5|||D0G4;|ATTR_Delay(D5G1;NPX3.5;Y-2;)I100|ATTR_X(D5G1.5;NPX3.5;Y0.5;)S10
+IorangeTSMC090nm:PMOSx;1{ic}|PMOSx@0||12|5|||D0G4;|ATTR_Delay(D5G1;NPX3.5;Y-2;)I100|ATTR_X(D5G1.5;NPX3.5;Y0.5;)S10
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NOff-Page|conn@0||-25|0||||
+NOff-Page|conn@1||34|0||||
+NOff-Page|conn@2||-25|-9||||
+IdataMux10;1{ic}|dataMux1@0||23|22.5|||D5G4;
+NGround|gnd@0||12|-12||||
+IredFive:inv;1{ic}|inv@0||27|0|||D0G4;|ATTR_Delay(D5G1;NPX2;Y-2;)I100|ATTR_X(D5G1.5;NPX1.5;Y2;)S10|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1
+IredFive:nms2b;1{ic}|nms2@0||-12|-9|||D0G4;|ATTR_Delay(D5G1;NPX3;Y-0.5;)I100|ATTR_X(D5G1.5;NOJPX-2.25;Y1.5;)S5|ATTR_LEGATE()I1|ATTR_LEPARALLGRP()I-1
+Ngeneric:Invisible-Pin|pin@0||1|35.5|||||ART_message(D5G6;)SdataMux10
+Ngeneric:Invisible-Pin|pin@1||-1|30.5|||||ART_message(D5G4;)Sthrough, zero or one
+Ngeneric:Invisible-Pin|pin@2||-2|25.5|||||ART_message(D5G3;)Sies 3 March 2008
+NWire_Pin|pin@6||-18|-9||||
+NWire_Pin|pin@7||-18|9||||
+NWire_Pin|pin@8||12|0||||
+NWire_Pin|pin@9||-12|0||||
+NWire_Pin|pin@10||-18|0||||
+NWire_Pin|pin@11||-3|5||||
+NWire_Pin|pin@13||-3|-5||||
+NWire_Pin|pin@15||3|5||||
+NWire_Pin|pin@16||3|12||||
+NWire_Pin|pin@17||3|-5||||
+NWire_Pin|pin@18||3|-12||||
+NWire_Pin|pin@19||-3|-12||||
+NWire_Pin|pin@22||-3|12||||
+Ngeneric:Invisible-Pin|pin@23||20|-10.5|||||ART_message(D6G2;)S["c[4],c[3],c[2],c[1]",only three values permitted,0 1 0 1   input,1 0 0 0   zero,1 0 1 1   one]
+IredFive:pms2;1{ic}|pms2@0||-12|9|||D0G4;|ATTR_Delay(D5G1;NPX-3;Y-1.5;)I100|ATTR_X(D5G1.5;NOLPX2.25;Y1;)S5
+NPower|pwr@0||12|12||||
+IorangeTSMC090nm:wire90;1{ic}|wire90@0||19|0|||D0G4;|ATTR_L(D5G1;PUD)D257.1|ATTR_LEWIRE(P)I1|ATTR_layer(D5G1;NPY-1;)I1|ATTR_width(D5G1;NPY-2;)I3
+Awire|c[1]|D5G2;||900|pin@17||3|-5|pin@18||3|-12
+Awire|c[2]|D5G2;||2700|pin@15||3|5|pin@16||3|12
+Awire|c[3]|D5G2;||2700|pin@19||-3|-12|pin@13||-3|-5
+Awire|c[4]|D5G2;||900|pin@22||-3|12|pin@11||-3|5
+Awire|net@6|||0|nms2@0|g|-15|-9|pin@6||-18|-9
+Awire|net@7|||2700|pin@10||-18|0|pin@7||-18|9
+Awire|net@8|||1800|pin@7||-18|9|pms2@0|g|-15|9
+Awire|net@11|||900|pin@9||-12|0|nms2@0|d|-12|-3
+Awire|net@12|||900|pin@8||12|0|NMOSx@0|d|12|-3
+Awire|net@14|||900|PMOSx@0|d|12|3|pin@8||12|0
+Awire|net@16|||900|pms2@0|d|-12|3|pin@9||-12|0
+Awire|net@17|||0|pin@8||12|0|pin@9||-12|0
+Awire|net@19|||2700|pin@6||-18|-9|pin@10||-18|0
+Awire|net@20|||1800|conn@0|y|-23|0|pin@10||-18|0
+Awire|net@21|||2700|gnd@0||12|-10|NMOSx@0|s|12|-7
+Awire|net@22|||2700|PMOSx@0|s|12|7|pwr@0||12|12
+Awire|net@23|||1800|pms2@0|g2|-9|5|pin@11||-3|5
+Awire|net@25|||1800|nms2@0|g2|-9|-5|pin@13||-3|-5
+Awire|net@27|||0|PMOSx@0|g|9|5|pin@15||3|5
+Awire|net@29|||0|NMOSx@0|g|9|-5|pin@17||3|-5
+Awire|net@40|||0|conn@1|a|32|0|inv@0|out|29.5|0
+Awire|net@41|||0|inv@0|in|24.5|0|wire90@0|b|21.5|0
+Awire|net@42|||0|wire90@0|a|16.5|0|pin@8||12|0
+Ec[1:4]||D4G2;|conn@2|a|I
+EinB[1]||D4G2;|conn@0|a|I
+Eout[1]||D6G2;|conn@1|y|O
+X