migrate jelib->delib

[fleet.git] / chips / marina / electric / latchesK.delib / latch1in10Am.lay

diff --git a/chips/marina/electric/latchesK.delib/latch1in10Am.lay b/chips/marina/electric/latchesK.delib/latch1in10Am.lay
new file mode 100644 (file)
index 0000000..4a61f08
--- /dev/null
+++ b/chips/marina/electric/latchesK.delib/latch1in10Am.lay
@@ -0,0 +1,36 @@
+HlatchesK|8.10k
+
+# External Libraries:
+
+LlatchPartsK|latchPartsK
+
+LwiresL|wiresL
+
+# Cell latch1in10Am;2{lay}
+Clatch1in10Am;2{lay}|latch1in10A|cmos90|1194236252807|1241212843263||ATTR_NCC(D5G3;NTY70;)S["exportsConnectedByParent vdd /vdd_[0-9]+/"]|DRC_last_good_drc_bit()I10|DRC_last_good_drc_date()G1241982414663
+Ngeneric:Facet-Center|art@0||0|0||||AV
+Iraw1inLatchF;1{lay}|hi1inLat@0||0|0|||D5G4;
+IlatchPartsK:latchAmp10;1{lay}|latchAmp@0||34|0|||D5G4;
+NMetal-1-Pin|pin@3||7.8|-25||||
+NMetal-2-Pin|pin@4||42|50||||
+IlatchPartsK:shoulderFillWide;1{lay}|shoulder@0||35|50|X||D5G4;
+IwiresL:wellContacts13;1{lay}|wellCont@1||17|0|||D5G4;
+Ametal-1|net@9|||S0|latchAmp@0|in|30.5|-25|pin@3||7.8|-25
+Ametal-2|net@14||6.2|S0|wellCont@1|vdd_1|12.5|50|hi1inLat@0|vdd_3|-0.2|50
+Ametal-2|net@15||6.2|S1800|hi1inLat@0|gnd_1|-0.2|0|wellCont@1|gnd|12.5|0
+Ametal-2|net@16||6.2|S1800|hi1inLat@0|vdd_4|-0.2|-50|wellCont@1|vdd|12.5|-50
+Ametal-2|net@17||6.2|S1800|wellCont@1|gnd_1|21.5|0|latchAmp@0|gnd|26|0
+Ametal-2|net@18||6.2|S0|latchAmp@0|vdd|26|-50|wellCont@1|vdd_2|21.5|-50
+Ametal-2|net@19||6.2|S0|pin@4||42|50|wellCont@1|vdd_3|21.5|50
+Ametal-1|net@20|||S2700|pin@3||7.8|-25|hi1inLat@0|out[F]|7.8|-12.5
+Egnd||D5G2;|hi1inLat@0|gnd|G
+Egnd_1||D5G2;|latchAmp@0|gnd_1|G
+Ehcl||D5G2;|hi1inLat@0|hcl|I
+Ehcl_1||D5G2;|hi1inLat@0|hcl_1|I
+Ein[1]||D5G2;|hi1inLat@0|in[1]|I
+Eout[1]||D5G2;|latchAmp@0|out[1]|O
+Evdd||D5G2;|hi1inLat@0|vdd|P
+Evdd_1||D5G2;|latchAmp@0|vdd_1|P
+Evdd_2||D5G2;|hi1inLat@0|vdd_2|P
+Evdd_3||D5G2;|pin@4||P
+X