migrate jelib->delib

[fleet.git] / chips / marina / electric / latchesK.delib / latch1in20Bm2dn.lay

diff --git a/chips/marina/electric/latchesK.delib/latch1in20Bm2dn.lay b/chips/marina/electric/latchesK.delib/latch1in20Bm2dn.lay
new file mode 100644 (file)
index 0000000..c256587
--- /dev/null
+++ b/chips/marina/electric/latchesK.delib/latch1in20Bm2dn.lay
@@ -0,0 +1,35 @@
+HlatchesK|8.10k
+
+# External Libraries:
+
+LlatchPartsK|latchPartsK
+
+# Cell latch1in20Bm2dn;2{lay}
+Clatch1in20Bm2dn;2{lay}|latch1in20B|cmos90|1197076555516|1241212843263||ATTR_NCC(D5G3;NTY70;)S["exportsConnectedByParent vdd /vdd_[0-9]+/",exportsConnectedByParent hcl hcl_1]|DRC_last_good_drc_bit()I10|DRC_last_good_drc_date()G1241982414663
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NX-Metal-1-Metal-2-Con|contact@0||-20.5|10||||
+NX-Metal-1-Metal-2-Con|contact@1||26.5|-10||||
+IlatchPartsK:latchAmp20B;1{lay}|latchAmp@2||22|0|||D5G4;
+NMetal-1-Pin|pin@30||0.8|-25||||
+NMetal-2-Pin|pin@32||-13|10||||
+NMetal-2-Pin|pin@34||15|-10||||
+Iraw1inLatchT;1{lay}|raw1inLa@1||-7|0|||D5G4;
+Ametal-2|net@84||6.2|S1800|raw1inLa@1|vdd_3|-7.2|50|latchAmp@2|vdd_2|9.5|50
+Ametal-2|net@85||6.2|S1800|raw1inLa@1|gnd_1|-7.2|0|latchAmp@2|gnd|9.5|0
+Ametal-2|net@86||6.2|S1800|raw1inLa@1|vdd_4|-7.2|-50|latchAmp@2|vdd|9.5|-50
+Ametal-1|net@87|||S900|raw1inLa@1|out[T]|0.8|-12.5|pin@30||0.8|-25
+Ametal-1|net@88|||S1800|pin@30||0.8|-25|latchAmp@2|in|13|-25
+Ametal-1|net@89|||S2700|raw1inLa@1|inA[1]|-20.5|-7|contact@0||-20.5|10
+Ametal-2|net@90|||S1800|contact@0||-20.5|10|pin@32||-13|10
+Ametal-1|net@91|||S900|latchAmp@2|out[1]|26.5|-7|contact@1||26.5|-10
+Ametal-2|net@92|||S0|contact@1||26.5|-10|pin@34||15|-10
+Egnd||D5G2;|raw1inLa@1|gnd|G
+Egnd_1||D5G2;|latchAmp@2|gnd_1|G
+Ehcl||D5G2;|raw1inLa@1|hcl[A]|I
+Ein[1]||D5G2;|pin@32||I
+Eout[1]||D5G2;|pin@34||O
+Evdd||D5G2;|raw1inLa@1|vdd|P
+Evdd_1||D5G2;|latchAmp@2|vdd_1|P
+Evdd_2||D5G2;|raw1inLa@1|vdd_2|P
+Evdd_3||D5G2;|latchAmp@2|vdd_3|P
+X