migrate jelib->delib

[fleet.git] / chips / marina / electric / latchesK.delib / latch2in60Cm3.lay

diff --git a/chips/marina/electric/latchesK.delib/latch2in60Cm3.lay b/chips/marina/electric/latchesK.delib/latch2in60Cm3.lay
new file mode 100644 (file)
index 0000000..9c03a66
--- /dev/null
+++ b/chips/marina/electric/latchesK.delib/latch2in60Cm3.lay
@@ -0,0 +1,43 @@
+HlatchesK|8.10k
+
+# External Libraries:
+
+LlatchPartsK|latchPartsK
+
+# Cell latch2in60Cm3;1{lay}
+Clatch2in60Cm3;1{lay}|latch2in60C|cmos90|1194627475361|1238257435226||ATTR_NCC(D5G3;NTY70;)S["exportsConnectedByParent vdd /vdd_[0-9]+/"]
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NX-Metal-1-Metal-2-Con|contact@1||-37|-28||||
+NX-Metal-1-Metal-2-Con|contact@2||-6|-28||||
+NX-Metal-1-Metal-2-Con|contact@3||-58.5|10||||
+NX-Metal-1-Metal-2-Con|contact@4||-31.5|10||||
+NX-Metal-2-Metal-3-Con|contact@5||-40|10||||
+NX-Metal-2-Metal-3-Con|contact@6||-52|10||||
+Iraw2inLatchF;1{lay}|hi2inLat@1||-45|0|||D5G4;
+IlatchPartsK:latchAmp60Cm3;1{lay}|latchAmp@0||40|0|||D5G4;
+NMetal-3-Pin|pin@0||-52|-13||||
+NMetal-3-Pin|pin@1||-40|-13||||
+Ametal-2|net@14||6.2|S0|latchAmp@0|vdd_1|-13.5|50|hi2inLat@1|vdd_3|-18|50
+Ametal-2|net@18|||S1800|contact@1||-37|-28|contact@2||-6|-28
+Ametal-1|net@23|||S900|latchAmp@0|in|-6|-24|contact@2||-6|-28
+Ametal-1|net@26|||S2700|hi2inLat@1|inA[1]|-58.5|-7|contact@3||-58.5|10
+Ametal-1|net@28|||S2700|hi2inLat@1|inB[1]|-31.5|-7|contact@4||-31.5|10
+Ametal-2|net@29|||S1800|contact@5||-40|10|contact@4||-31.5|10
+Ametal-3|net@30|||S2700|pin@1||-40|-13|contact@5||-40|10
+Ametal-2|net@31|||S1800|contact@3||-58.5|10|contact@6||-52|10
+Ametal-3|net@32|||S2700|pin@0||-52|-13|contact@6||-52|10
+Ametal-1|net@33|||S2700|contact@1||-37|-28|hi2inLat@1|out[F]|-37|-12.5
+Ametal-2|net@40||6.2|S1800|hi2inLat@1|gnd_1|-18|0|latchAmp@0|gnd|-13.5|0
+Ametal-2|net@41||6.2|S0|latchAmp@0|vdd|-13.5|-50|hi2inLat@1|vdd_4|-18|-50
+Egnd||D5G2;|hi2inLat@1|gnd|G
+Egnd_1||D5G2;|latchAmp@0|gnd_1|G
+Ehcl[A]||D5G2;|hi2inLat@1|hcl[A]|I
+Ehcl[B]||D5G2;|hi2inLat@1|hcl[B]|I
+EinA[1]||D5G2;|pin@0||I
+EinB[1]||D5G2;|pin@1||I
+Eout[1]|outS[1]|D5G2;|latchAmp@0|out[1]|O
+Evdd||D5G2;|hi2inLat@1|vdd|P
+Evdd_2||D5G2;|hi2inLat@1|vdd_2|P
+Evdd_3||D5G2;|latchAmp@0|vdd_2|P
+Evdd_4||D5G2;|latchAmp@0|vdd_3|P
+X