migrate jelib->delib

[fleet.git] / chips / marina / electric / latchesK.delib / plat1in10.sch

diff --git a/chips/marina/electric/latchesK.delib/plat1in10.sch b/chips/marina/electric/latchesK.delib/plat1in10.sch
new file mode 100644 (file)
index 0000000..769e146
--- /dev/null
+++ b/chips/marina/electric/latchesK.delib/plat1in10.sch
@@ -0,0 +1,74 @@
+HlatchesK|8.10k
+
+# External Libraries:
+
+LorangeTSMC090nm|orangeTSMC090nm
+
+LredFive|redFive
+
+# Cell plat1in10;1{sch}
+Cplat1in10;1{sch}||schematic|1204973663598|1211406973750|
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NOff-Page|conn@1||36|0||||
+NOff-Page|conn@2||-12|-18|||YRRR|
+NOff-Page|conn@4||3|-18|||R|
+IredFive:inv;1{ic}|inv@1||24|0|||D0G4;|ATTR_Delay(D5G1;NPX2;Y-2;)I100|ATTR_X(D5FLeave alone;G1.5;NPX1.5;Y2;)S10|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1
+IredFive:nms2b;1{ic}|nms2@0||12|-9|X||D0G4;|ATTR_Delay(D5G1;NPX3;Y-0.5;)I100|ATTR_X(D5G1.5;NOJPX-2.25;Y1.5;)S2
+IredFive:nms2b;1{ic}|nms2@1||-6|-9|||D0G4;|ATTR_Delay(D5G1;NPX3;Y-0.5;)I100|ATTR_X(D5G1.5;NOJPX-2.25;Y1.5;)S5
+Ngeneric:Invisible-Pin|pin@0||0|24.5|||||ART_message(D5G3;)Sies 21 May 2008
+Ngeneric:Invisible-Pin|pin@1||0|28.5|||||ART_message(D5G4;)Sstronger pass gate 1 input latch
+Ngeneric:Invisible-Pin|pin@2||0|33.5|||||ART_message(D5G6;)Splat1in10
+NWire_Pin|pin@7||12|0||||
+NWire_Pin|pin@20||1|-2||||
+NWire_Pin|pin@21||5|2||||
+NWire_Pin|pin@22||5|-2|||X|
+NWire_Pin|pin@23||1|2|||X|
+NWire_Pin|pin@25||30|0||||
+NWire_Pin|pin@37||5|5||||
+NWire_Pin|pin@38||5|-5||||
+NWire_Pin|pin@41||-12|9||||
+NWire_Pin|pin@52||-6|0||||
+NWire_Pin|pin@54||-12|-9||||
+NWire_Pin|pin@55||1|-5||||
+NWire_Pin|pin@57||1|5||||
+NWire_Pin|pin@58||30|-9||||
+NWire_Pin|pin@59||30|9||||
+NWire_Pin|pin@66||1|-12.5||||
+NWire_Pin|pin@67||1|11.5||||
+Iplat1in10;1{ic}|plat1in1@0||28|20|||D5G4;
+IredFive:pms2;1{ic}|pms2@0||12|9|X||D0G4;|ATTR_Delay(D5G1;NPX-3;Y-1.5;)I100|ATTR_X(D5G1.5;NOLPX2.25;Y1;)S1
+IredFive:pms2;1{ic}|pms2@1||-6|9|||D0G4;|ATTR_Delay(D5G1;NPX-3;Y-1.5;)I100|ATTR_X(D5G1.5;NOLPX2.25;Y1;)S5
+IorangeTSMC090nm:wire90;1{ic}|wire90@0||17.5|0|||D0G4;|ATTR_L(D5FLeave alone;G1;PUD)D205.89999999999998|ATTR_LEWIRE(P)I1|ATTR_layer(D5G1;NPY-1;)I1|ATTR_width(D5G1;NPY-2;)I3
+Awire|c[F]|D5G2;||2700|pin@57||1|5|pin@67||1|11.5
+Awire|c[T]|D5G2;||900|pin@55||1|-5|pin@66||1|-12.5
+Awire|net@4|||2700|pin@7||12|0|pms2@0|d|12|3
+Awire|net@11|||2700|nms2@0|d|12|-3|pin@7||12|0
+Awire|net@12|||0|wire90@0|a|15|0|pin@7||12|0
+Awire|net@25|||0|conn@1|a|34|0|pin@25||30|0
+Awire|net@26|||0|inv@1|in|21.5|0|wire90@0|b|20|0
+Awire|net@30|||2250|pin@20||1|-2|pin@21||5|2
+Awire|net@31|||3150|pin@22||5|-2|pin@23||1|2
+Awire|net@33|||0|pin@25||30|0|inv@1|out|26.5|0
+Awire|net@34|||2700|pin@58||30|-9|pin@25||30|0
+Awire|net@54|||2700|pin@21||5|2|pin@37||5|5
+Awire|net@55|||1800|pin@37||5|5|pms2@0|g2|9|5
+Awire|net@56|||900|pin@22||5|-2|pin@38||5|-5
+Awire|net@57|||1800|pin@38||5|-5|nms2@0|g2|9|-5
+Awire|net@68|||1800|pin@41||-12|9|pms2@1|g|-9|9
+Awire|net@84|||900|pin@52||-6|0|nms2@1|d|-6|-3
+Awire|net@85|||900|pms2@1|d|-6|3|pin@52||-6|0
+Awire|net@86|||0|pin@7||12|0|pin@52||-6|0
+Awire|net@87|||2700|pin@23||1|2|pin@57||1|5
+Awire|net@88|||2700|pin@54||-12|-9|pin@41||-12|9
+Awire|net@89|||2700|conn@2|y|-12|-16|pin@54||-12|-9
+Awire|net@90|||0|nms2@1|g|-9|-9|pin@54||-12|-9
+Awire|net@91|||1800|nms2@1|g2|-3|-5|pin@55||1|-5
+Awire|net@92|||2700|pin@55||1|-5|pin@20||1|-2
+Awire|net@97|||0|pin@57||1|5|pms2@1|g2|-3|5
+Awire|net@101|||900|pin@59||30|9|pin@25||30|0
+Awire|net@102|||1800|nms2@0|g|15|-9|pin@58||30|-9
+Awire|net@112|||1800|pms2@0|g|15|9|pin@59||30|9
+Ecl[T,F]|c[T,F]|D4G2;|conn@4|a|I
+Ein||D4G2;|conn@2|a|I
+Eout||D6G2;|conn@1|y|O
+X