migrate jelib->delib

[fleet.git] / chips / marina / electric / latchesK.delib / raw1inLatchF.sch

diff --git a/chips/marina/electric/latchesK.delib/raw1inLatchF.sch b/chips/marina/electric/latchesK.delib/raw1inLatchF.sch
new file mode 100644 (file)
index 0000000..1852e8b
--- /dev/null
+++ b/chips/marina/electric/latchesK.delib/raw1inLatchF.sch
@@ -0,0 +1,45 @@
+HlatchesK|8.10k
+
+# External Libraries:
+
+LlatchPartsK|latchPartsK
+
+LorangeTSMC090nm|orangeTSMC090nm
+
+# Cell raw1inLatchF;1{sch}
+Craw1inLatchF;1{sch}||schematic|1194181042341|1205533351671|
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NOff-Page|conn@0||9|0||||
+NOff-Page|conn@1||-18|6||||
+NOff-Page|conn@2||-18|12||||
+Iraw1inLatchF;1{ic}|hi2inLat@0||12.5|11.5|||D5G4;
+IlatchPartsK:latchKeep;1{ic}|latchFlo@0||0|0|||D5G4;
+IlatchPartsK:latchPointF;1{ic}|latchPoi@0||-8|6|||D5G4;
+Ngeneric:Invisible-Pin|pin@13||1.5|28|||||ART_message(D5G6;)Sraw1inLatchF
+Ngeneric:Invisible-Pin|pin@14||0.5|19|||||ART_message(D5G3;)Sies 9 November 2007
+Ngeneric:Invisible-Pin|pin@15||-0.5|23|||||ART_message(D5G4;)SFALSE output latch
+NWire_Pin|pin@16||-10|12||||
+NWire_Pin|pin@18||4|7||||
+NWire_Pin|pin@20||4|0||||
+NWire_Pin|pin@23||-4|5||||
+NWire_Pin|pin@24||-4|2||||
+NWire_Pin|pin@25||-13|2||||
+NWire_Pin|pin@26||-13|0||||
+IorangeTSMC090nm:wire90;1{ic}|wire90@0||-9|0|||D0G4;|ATTR_L(D5G1;PUD)D146.10000000000002|ATTR_LEWIRE(P)I1|ATTR_layer(D5G1;NPY-1;)I1|ATTR_width(D5G1;NPY-2;)I3
+Awire|net@21|||1800|conn@1|y|-16|6|latchPoi@0|in[1]|-11|6
+Awire|net@22|||1800|conn@2|y|-16|12|pin@16||-10|12
+Awire|net@23|||900|pin@16||-10|12|latchPoi@0|hcl|-10|9
+Awire|net@37|||1800|latchPoi@0|x[F]|3|7|pin@18||4|7
+Awire|net@40|||900|pin@18||4|7|pin@20||4|0
+Awire|net@41|||1800|pin@20||4|0|conn@0|a|7|0
+Awire|net@45|||0|pin@23||-4|5|latchPoi@0|x[T]|-5|5
+Awire|net@48|||2700|pin@24||-4|2|pin@23||-4|5
+Awire|net@51|||0|pin@24||-4|2|pin@25||-13|2
+Awire|net@52|||900|pin@25||-13|2|pin@26||-13|0
+Awire|net@53|||1800|pin@26||-13|0|wire90@0|a|-11.5|0
+Awire|net@57|||0|pin@20||4|0|latchFlo@0|out[B]|2|0
+Awire|net@58|||0|latchFlo@0|out[s]|-2|0|wire90@0|b|-6.5|0
+Ehcl||D4G2;|conn@2|a|I
+Ein[1]||D4G2;|conn@1|a|I
+Eout[F]||D6G2;|conn@0|y|O
+X