migrate jelib->delib

[fleet.git] / chips / marina / electric / latchesK.delib / raw1inLatchT.lay

diff --git a/chips/marina/electric/latchesK.delib/raw1inLatchT.lay b/chips/marina/electric/latchesK.delib/raw1inLatchT.lay
new file mode 100644 (file)
index 0000000..7db40de
--- /dev/null
+++ b/chips/marina/electric/latchesK.delib/raw1inLatchT.lay
@@ -0,0 +1,43 @@
+HlatchesK|8.10k
+
+# External Libraries:
+
+LlatchPartsK|latchPartsK
+
+# Cell raw1inLatchT;1{lay}
+Craw1inLatchT;1{lay}||cmos90|1194182014255|1241981698008||ATTR_NCC(D5G3;NTY70;)S["exportsConnectedByParent vdd /vdd_[0-9]+/"]|DRC_last_good_drc_bit()I10|DRC_last_good_drc_date()G1241981826991
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NX-Metal-1-Metal-2-Con|contact@0||-5|28||||
+NX-Metal-1-Metal-2-Con|contact@3||7.8|28||||
+IlatchPartsK:latchKeep;1{lay}|latchFlo@0||-0.2|0|||D5G4;
+IlatchPartsK:latchPointT;1{lay}|latchPoi@3||-19|0|||D5G4;
+NMetal-1-Pin|pin@4||0.5|13||||
+NMetal-1-Pin|pin@5||-8.2|13||||
+NMetal-2-Pin|pin@7||-27|50||||
+NMetal-2-Pin|pin@8||-0.2|50||||
+NMetal-1-Pin|pin@21||-5|31.5||||
+NMetal-1-Pin|pin@22||0.5|43.5||||
+IlatchPartsK:shoulderFill;1{lay}|shoulder@0||-27|50|||D5G4;
+IlatchPartsK:shoulderFillNarrow;1{lay}|shoulder@1||8.5|50|X||D5G4;
+Ametal-1|net@5|||S900|pin@22||0.5|43.5|pin@4||0.5|13
+Ametal-1|net@6|||S0|pin@4||0.5|13|pin@5||-8.2|13
+Ametal-1|net@7|||S900|pin@5||-8.2|13|latchFlo@0|out[s]|-8.2|-13
+Ametal-2|net@18|||S1800|contact@0||-5|28|contact@3||7.8|28
+Ametal-1|net@76|||S2700|latchFlo@0|out[B]|7.8|-12.5|contact@3||7.8|28
+Ametal-1|net@80|||S2700|contact@0||-5|28|pin@21||-5|31.5
+Ametal-1|net@81|||S900|latchPoi@3|x[T]|-5|31.5|pin@21||-5|31.5
+Ametal-2|net@87||6.2|S1800|pin@7||-27|50|pin@8||-0.2|50
+Ametal-2|net@88||6.2|S0|latchFlo@0|gnd|-0.2|0|latchPoi@3|gnd|-27|0
+Ametal-2|net@89||6.2|S1800|latchPoi@3|vdd|-27|-50|latchFlo@0|vdd|-0.2|-50
+Ametal-1|net@93|||S0|pin@22||0.5|43.5|latchPoi@3|x[F]|-5|43.5
+Egnd||D5G2;|latchPoi@3|gnd|G
+Egnd_1||D5G2;|latchFlo@0|gnd|G
+Ehcl[A]||D5G2;|latchPoi@3|hcl|I
+Ehcl_1||D5G2;|latchPoi@3|hcl_1|I
+EinA[1]||D5G2;|latchPoi@3|in[1]|I
+Eout[T]||D5G2;|latchFlo@0|out[B]|I
+Evdd||D5G2;|latchPoi@3|vdd|P
+Evdd_2||D5G2;|pin@7||P
+Evdd_3||D5G2;|pin@8||P
+Evdd_4||D5G2;|latchFlo@0|vdd|P
+X