migrate jelib->delib

[fleet.git] / chips / marina / electric / latchesK.delib / raw1inLatchT.sch

diff --git a/chips/marina/electric/latchesK.delib/raw1inLatchT.sch b/chips/marina/electric/latchesK.delib/raw1inLatchT.sch
new file mode 100644 (file)
index 0000000..8ef60bd
--- /dev/null
+++ b/chips/marina/electric/latchesK.delib/raw1inLatchT.sch
@@ -0,0 +1,45 @@
+HlatchesK|8.10k
+
+# External Libraries:
+
+LlatchPartsK|latchPartsK
+
+LorangeTSMC090nm|orangeTSMC090nm
+
+# Cell raw1inLatchT;1{sch}
+Craw1inLatchT;1{sch}||schematic|1194181042341|1206032620336|
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NOff-Page|conn@0||9|-1||||
+NOff-Page|conn@1||-18|6||||
+NOff-Page|conn@2||-18|12||||
+Iraw1inLatchT;1{ic}|hi2inLat@0||11|13|||D5G4;
+IlatchPartsK:latchKeep;1{ic}|latchFlo@0||0|-1|||D5G4;
+IlatchPartsK:latchPointT;1{ic}|latchPoi@0||-8|6|||D5G4;
+NWire_Pin|pin@6||-4|5||||
+NWire_Pin|pin@8||4|7||||
+NWire_Pin|pin@10||4|-1||||
+Ngeneric:Invisible-Pin|pin@13||0|28|||||ART_message(D5G6;)Sraw1inLatchT
+Ngeneric:Invisible-Pin|pin@14||0|19|||||ART_message(D5G3;)Sies 4 November 2007
+Ngeneric:Invisible-Pin|pin@15||0|23|||||ART_message(D5G4;)STRUE output latch
+NWire_Pin|pin@16||-10|12||||
+NWire_Pin|pin@17||-4|2||||
+NWire_Pin|pin@18||-13|2||||
+NWire_Pin|pin@19||-13|-1||||
+IorangeTSMC090nm:wire90;1{ic}|wire90@0||-8|-1|||D0G4;|ATTR_L(D5G1;PUD)D180.9|ATTR_LEWIRE(P)I1|ATTR_layer(D5G1;NPY-1;)I1|ATTR_width(D5G1;NPY-2;)I3
+Awire|net@7|||0|pin@6||-4|5|latchPoi@0|x[F]|-5|5
+Awire|net@11|||1800|latchPoi@0|x[T]|3|7|pin@8||4|7
+Awire|net@12|||900|pin@8||4|7|pin@10||4|-1
+Awire|net@19|||1800|latchFlo@0|out[B]|2|-1|pin@10||4|-1
+Awire|net@20|||0|conn@0|a|7|-1|pin@10||4|-1
+Awire|net@21|||1800|conn@1|y|-16|6|latchPoi@0|in[1]|-11|6
+Awire|net@22|||1800|conn@2|y|-16|12|pin@16||-10|12
+Awire|net@23|||900|pin@16||-10|12|latchPoi@0|hcl|-10|9
+Awire|net@25|||2700|pin@17||-4|2|pin@6||-4|5
+Awire|net@26|||0|pin@17||-4|2|pin@18||-13|2
+Awire|net@27|||900|pin@18||-13|2|pin@19||-13|-1
+Awire|net@28|||1800|pin@19||-13|-1|wire90@0|a|-10.5|-1
+Awire|net@29|||0|latchFlo@0|out[s]|-2|-1|wire90@0|b|-5.5|-1
+Ehcl[A]||D4G2;|conn@2|a|I
+EinA[1]||D4G2;|conn@1|a|I
+Eout[T]||D6G2;|conn@0|y|O
+X