move marina directory into a subdirectory of chips
[fleet.git] / chips / marina / electric / marina_padframe.delib / PVSS3CDG_18.ic
diff --git a/chips/marina/electric/marina_padframe.delib/PVSS3CDG_18.ic b/chips/marina/electric/marina_padframe.delib/PVSS3CDG_18.ic
new file mode 100755 (executable)
index 0000000..45620e9
--- /dev/null
@@ -0,0 +1,42 @@
+Hmarina_padframe|8.09a
+
+# Cell PVSS3CDG_18;1{ic}
+CPVSS3CDG_18;1{ic}||artwork|1185234419494|1241276241816|EI
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NOpened-Thicker-Polygon|art@1||0|1|14|20|||SCHEM_function(D5G2;Y-11;)SPVSS3CDG_18|trace()V[-7/-10,-7/10,7/10,7/-10,-7/-10]
+NOpened-Dashed-Polygon|art@3||-3|-1.5|2|11|||trace()V[0/-5.5,-1/-5.5,-1/5.5,1/5.5]
+NOpened-Dashed-Polygon|art@4||3|-1.5|2|11|X||trace()V[0/-5.5,-1/-5.5,-1/5.5,1/5.5]
+NOpened-Dashed-Polygon|art@5||-3.5|7|1|6|||trace()V[-0.5/-3,-0.5/3,0.5/3]
+NOpened-Dashed-Polygon|art@6||3.5|7|1|6|X||trace()V[-0.5/-3,-0.5/3,0.5/3]
+NOpened-Thicker-Polygon|art@7||-3|1.5|2|3|||trace()V[0/0,1/-0.5,1/-1.5,-0.5/-1.5,-1/-1,-1/1,-0.5/1.5,1/1.5]
+NOpened-Thicker-Polygon|art@8||0|1.5|2|3|||trace()V[-1/-1.5,-1/1.5,1/-1.5,1/1.5]
+NOpened-Thicker-Polygon|art@9||3|1.5|2|3|||trace()V[-1/-1.5,-1/1.5,0.5/1.5,1/1,1/-1,0.5/-1.5,-1/-1.5]
+Nschematic:Bus_Pin|pin@0||-7|0||||
+Nschematic:Bus_Pin|pin@2||7|0||||
+Nschematic:Bus_Pin|pin@4||-7|7||||
+Nschematic:Bus_Pin|pin@6||-7|-4||||
+Nschematic:Bus_Pin|pin@8||7|-4||||
+Nschematic:Bus_Pin|pin@10||7|7||||
+Nschematic:Bus_Pin|pin@12||0|11||||
+Nschematic:Bus_Pin|pin@14||-7|4||||
+Nschematic:Bus_Pin|pin@16||-7|-7||||
+Nschematic:Bus_Pin|pin@18||7|-7||||
+Nschematic:Bus_Pin|pin@20||7|4||||
+Ngeneric:Invisible-Pin|pin@21||0|7|||||ART_message(D5G1;)SVDD
+Ngeneric:Invisible-Pin|pin@22||0|4|||||ART_message(D5G1;)SVSS
+Ngeneric:Invisible-Pin|pin@23||0|0|||||ART_message(D5G1;)SPOC18
+Ngeneric:Invisible-Pin|pin@24||0|-4|||||ART_message(D5G1;)SVDDPST18
+Ngeneric:Invisible-Pin|pin@25||0|-7|||||ART_message(D5G1;)SVSSPST18
+Ngeneric:Invisible-Pin|pin@26||0|10|||||ART_message(D5G1;)SVSS_CORE
+EPOC18||D5G2;|pin@0||B
+EPOC18_1||D5G2;|pin@2||B
+EVDD||D5G2;|pin@4||P
+EVDDPST18||D5G2;|pin@6||P
+EVDDPST18_1||D5G2;|pin@8||P
+EVDD_1||D5G2;|pin@10||P
+EVSS||D5G2;|pin@14||G
+EVSSPST18||D5G2;|pin@16||G
+EVSSPST18_1||D5G2;|pin@18||G
+EVSS_1||D5G2;|pin@20||G
+EVDD_2|VSS_2|D5G2;|pin@12||G
+X