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migrate jelib->delib
[fleet.git] / chips / marina / electric / oneHotM.delib / minusOne.sch
diff --git a/chips/marina/electric/oneHotM.delib/minusOne.sch b/chips/marina/electric/oneHotM.delib/minusOne.sch
new file mode 100644 (file)
index 0000000..abe499b
--- /dev/null
+++ b/chips/marina/electric/oneHotM.delib/minusOne.sch
@@ -0,0 +1,113 @@
+HoneHotM|8.10k
+
+# External Libraries:
+
+LdriversM|driversM
+
+LorangeTSMC090nm|orangeTSMC090nm
+
+LredFive|redFive
+
+# Cell minusOne;2{sch}
+CminusOne;2{sch}||schematic|1227919307257|1240925657717|
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NOff-Page|conn@6||-29.25|26||||
+NOff-Page|conn@8||0|33|||XR|
+NOff-Page|conn@9||41.5|11|||XRR|
+NOff-Page|conn@10||-11|33|||RRR|
+NOff-Page|conn@11||-1|-30|||XRRR|
+NOff-Page|conn@12||-29.25|6||||
+NOff-Page|conn@13||40.5|24||||
+NOff-Page|conn@14||-29.25|9||||
+IredFive:inv;1{ic}|inv@7||-18|-15|||D0G4;|ATTR_Delay(D5G1;NPX2;Y-2;)I100|ATTR_X(D5G1.5;NPX1.5;Y2;)S5|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1
+IredFive:invI;2{ic}|invI@0||-1|-21|RRR||D0G4;|ATTR_Delay(D5G1;NPX2;Y-2;)I100|ATTR_X(D5G1.5;NPX1.5;Y2;)S10|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1
+IredFive:invI;2{ic}|invI@1||-9|17.5|R||D0G4;|ATTR_Delay(D5G1;NPX2;Y-2;)I100|ATTR_X(D5G1.5;NPX1.5;Y2;)S10|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1
+IminusOne;1{ic}|minusOne@0||42|40|||D5G4;
+IredFive:nand2;1{ic}|nand2@1||-9|1|R||D0G4;|ATTR_Delay(D5G1;NPX2.5;Y-3;)I100|ATTR_X(D5G1.5;NPX2.5;Y2.5;)S10|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1
+IredFive:nor2n;1{ic}|nor2n@0||6|12|Y||D0G4;|ATTR_Delay(D5G1;NPX3;Y-3;)I100|ATTR_X(D5G1.5;NPX2.25;Y2.25;)S20|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1
+IredFive:nor2n_sy;1{ic}|nor2n_sy@1||0|-11|R||D0G4;|ATTR_Delay(D5G1;NPX3;Y-3;)I100|ATTR_X(D5FLeave alone;G1.5;NOLPX2.25;Y2.25;)S5|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1
+Ngeneric:Invisible-Pin|pin@16||0|62.5|||||ART_message(D5G5;)SminusOne
+Ngeneric:Invisible-Pin|pin@17||0.5|58.5|||||ART_message(D5G3;)Sies 16 February 2009
+Ngeneric:Invisible-Pin|pin@108||2|54|||||ART_message(D5G2;)S[The stage before On Deck,sends instructions to two places.]
+NWire_Pin|pin@112||0|24||||
+NWire_Pin|pin@114||-11|28||||
+NWire_Pin|pin@115||-1|-15||||
+NWire_Pin|pin@116||-24|26||||
+NWire_Pin|pin@118||-24|-15||||
+NBus_Pin|pin@139||15|10|-1|-1||
+NBus_Pin|pin@140||15|5|-1|-1||
+Ngeneric:Invisible-Pin|pin@161||39.5|8|||||ART_message(D3G2;)S["m1cate[1:6][T,F] set by",the predicate bits of,this instruction.]
+NWire_Pin|pin@175||1|-15||||
+NWire_Pin|pin@177||33.5|-15||||
+NWire_Pin|pin@179||33.5|24||||
+Ngeneric:Invisible-Pin|pin@185||-5|49|||||ART_message(D3G2;)S[M1 sends all instructions to OD,via the succ state wire.,M1 sends all but HEAD instructions,to PS via the 12 m1cate wires.]
+NWire_Pin|pin@186||0|-6||||
+NWire_Pin|pin@195||-10|-6||||
+NWire_Pin|pin@196||-8|-3||||
+NWire_Pin|pin@197||-9|11||||
+NWire_Pin|pin@198||-9|24||||
+Ngeneric:Invisible-Pin|pin@199||38|-5|||||ART_message(D3G2;)S["m1cate[1][T,F] are",timing exemplars for,all m1cate bits.]
+NWire_Pin|pin@200||0|13||||
+NWire_Pin|pin@201||0|17||||
+NWire_Pin|pin@203||17|5||||
+NWire_Pin|pin@205||17|-3||||
+IdriversM:predDri20wMC;1{ic}|predDri2@0||-17|26|XY||D5G4;
+IsucDri10Pairx6;1{ic}|sucDri10@1||25|11|||D5G4;
+IdriversM:sucDri20;1{ic}|sucDri20@1||24.5|24|||D5G4;
+IorangeTSMC090nm:wire90;1{ic}|wire90@10||7|24|||D0G4;|ATTR_L(D5G1;PUD)D425.79999999999995|ATTR_LEWIRE(P)I1|ATTR_layer(D5G1;NPY-1;)I1|ATTR_width(D5G1;NPY-2;)I3
+IorangeTSMC090nm:wire90;1{ic}|wire90@11||-8|-15|||D0G4;|ATTR_L(D5G1;PUD)D257.29999999999995|ATTR_LEWIRE(P)I1|ATTR_layer(D5G1;NPY-1;)I1|ATTR_width(D5G1;NPY-2;)I3
+IorangeTSMC090nm:wire90;1{ic}|wire90@12||7|-3|||D0G4;|ATTR_L(D5G1;PUD)D692.6999999999999|ATTR_LEWIRE(P)I1|ATTR_layer(D5G1;NPY-1;)I1|ATTR_width(D5G1;NPY-2;)I3
+IorangeTSMC090nm:wire90;1{ic}|wire90@13||-6|-6|||D0G4;|ATTR_L(D5G1;PUD)D399.29999999999995|ATTR_LEWIRE(P)I1|ATTR_layer(D5G1;NPY-1;)I1|ATTR_width(D5G1;NPY-2;)I3
+IorangeTSMC090nm:wire90;1{ic}|wire90@14||-3|11|||D0G4;|ATTR_L(D5G1;PUD)D489.19999999999993|ATTR_LEWIRE(P)I1|ATTR_layer(D5G1;NPY-1;)I1|ATTR_width(D5G1;NPY-2;)I3
+IorangeTSMC090nm:wire90;1{ic}|wire90@15||14|12|||D0G4;|ATTR_L(D5G1;PUD)D1763.0000000000002|ATTR_LEWIRE(P)I1|ATTR_layer(D5G1;NPY-1;)I1|ATTR_width(D5G1;NPY-2;)I3
+Abus|bit[1:6]|D5G2;|-0.5|IJ900|pin@139||15|10|pin@140||15|5
+Awire|headBit|D5G2;||2700|pin@200||0|13|pin@201||0|17
+Awire|net@227|||0|wire90@10|a|4.5|24|pin@112||0|24
+Awire|net@232|||1800|predDri2@0|mc|-14|28|pin@114||-11|28
+Awire|net@235|||1800|wire90@11|b|-5.5|-15|pin@115||-1|-15
+Awire|net@238|||1800|pin@116||-24|26|predDri2@0|pred|-20|26
+Awire|net@239|||1800|conn@6|y|-27.25|26|pin@116||-24|26
+Awire|net@242|||1800|pin@118||-24|-15|inv@7|in|-20.5|-15
+Awire|net@251|||900|pin@116||-24|26|pin@118||-24|-15
+Awire|net@312|||2700|pin@114||-11|28|conn@10|y|-11|31
+Awire|net@313|||1800|inv@7|out|-15.5|-15|wire90@11|a|-10.5|-15
+Awire|net@314|||2700|invI@0|in|-1|-18.5|pin@115||-1|-15
+Awire|net@317|||2700|conn@11|a|-1|-28|invI@0|out|-1|-23.5
+Awire|net@345|||0|pin@179||33.5|24|sucDri20@1|succ|28.5|24
+Awire|net@346|||2700|pin@112||0|24|conn@8|a|0|31
+Abus|net@363||-0.5|IJ0|sucDri10@1|bit[1:6]|20|10|pin@139||15|10
+Abus|net@366||-0.5|IJ1800|sucDri10@1|m1cate[1:6][T,F]|30|11|conn@9|a|39.5|11
+Awire|net@377|||0|conn@13|a|38.5|24|pin@179||33.5|24
+Awire|net@379|||1800|pin@175||1|-15|pin@177||33.5|-15
+Awire|net@387|||2700|pin@177||33.5|-15|pin@179||33.5|24
+Awire|net@389|||900|nor2n_sy@1|inb|-1|-13.5|pin@115||-1|-15
+Awire|net@390|||900|nor2n_sy@1|ina|1|-13.5|pin@175||1|-15
+Awire|net@391|||1800|wire90@13|b|-3.5|-6|pin@186||0|-6
+Awire|net@392|||900|pin@186||0|-6|nor2n_sy@1|out|0|-8.5
+Awire|net@398|||1800|pin@197||-9|11|wire90@14|a|-5.5|11
+Awire|net@403|||0|pin@112||0|24|pin@198||-9|24
+Awire|net@405|||1800|wire90@14|b|-0.5|11|nor2n@0|inb|3.5|11
+Awire|net@406|||0|wire90@15|a|11.5|12|nor2n@0|out|8.5|12
+Awire|net@407|||0|sucDri20@1|in|20.5|24|wire90@10|b|9.5|24
+Awire|net@411|||900|nand2@1|inb|-10|-1.5|pin@195||-10|-6
+Awire|net@414|||2700|pin@196||-8|-3|nand2@1|ina|-8|-1.5
+Awire|net@415|||0|wire90@12|a|4.5|-3|pin@196||-8|-3
+Awire|net@416|||0|wire90@13|a|-8.5|-6|pin@195||-10|-6
+Awire|net@419|||2700|nand2@1|out|-9|3.5|pin@197||-9|11
+Awire|net@421|||0|sucDri10@1|when|20|12|wire90@15|b|16.5|12
+Awire|net@422|||2700|pin@197||-9|11|invI@1|in|-9|15
+Awire|net@423|||0|pin@198||-9|24|predDri2@0|in|-14|24
+Awire|net@424|||2700|invI@1|out|-9|20|pin@198||-9|24
+Awire|net@425|||0|nor2n@0|ina|3.5|13|pin@200||0|13
+Awire|net@435|||1800|wire90@12|b|9.5|-3|pin@205||17|-3
+Awire|net@436|||0|sucDri10@1|ready|25|5|pin@203||17|5
+Awire|net@440|||900|pin@203||17|5|pin@205||17|-3
+Ebit[1:6]||D4G2;|conn@12|a|I
+Efire[m1]||D6G2;|conn@8|y|O
+Epred_1|headBit|D4G2;|conn@14|a|I
+Em1cate[1:6][T,F]||D6G2;|conn@9|y|O
+Emc||D4G2;|conn@10|a|I
+Epred||D4G2;|conn@6|a|I
+Es[1]||D6G2;|conn@11|y|O
+Esucc|succ[m1]|D6G2;|conn@13|y|O
+X
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