migrate jelib->delib

[fleet.git] / chips / marina / electric / oneHotM.delib / minusOneStrong.lay

diff --git a/chips/marina/electric/oneHotM.delib/minusOneStrong.lay b/chips/marina/electric/oneHotM.delib/minusOneStrong.lay
new file mode 100644 (file)
index 0000000..93f99dc
--- /dev/null
+++ b/chips/marina/electric/oneHotM.delib/minusOneStrong.lay
@@ -0,0 +1,65 @@
+HoneHotM|8.10k
+
+# Cell minusOneStrong;1{lay}
+CminusOneStrong;1{lay}||cmos90|1240926056446|1241212843263||ATTR_NCC(D5G3;NTY140;)S["exportsConnectedByParent vdd /vdd_[0-9]+/","exportsConnectedByParent gnd /gnd_[0-9]+/"]
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NX-Metal-1-Metal-2-Con|contact@18||-14|-50||||
+NX-Metal-1-Metal-2-Con|contact@19||24.5|-50||||
+IminusOneGasP;1{lay}|minusOne@0||0|-72|||D5G4;
+NMetal-1-Pin|pin@24||3.5|6||||
+NMetal-1-Pin|pin@25||-14|0||||
+NMetal-1-Pin|pin@27||-25|0||||
+NMetal-1-Pin|pin@28||45.5|6||||
+NMetal-1-Pin|pin@30||45.5|47.5||||
+NMetal-1-Pin|pin@31||3.5|-40||||
+NMetal-1-Pin|pin@32||9.5|-40||||
+IsucDri10Pairx6s;1{lay}|sucDri10@0||-360|72|||D5G4;
+Ametal-1|net@120|||S900|minusOne@0|ready|24.5|-47|contact@19||24.5|-50
+Ametal-2|net@122|||S1800|contact@18||-14|-50|contact@19||24.5|-50
+Ametal-1|net@123|||S2700|contact@18||-14|-50|pin@25||-14|0
+Ametal-1|net@126|||S2700|pin@27||-25|0|sucDri10@0|out_4|-25|34
+Ametal-1|net@127|||S0|pin@25||-14|0|pin@27||-25|0
+Ametal-1|net@131|||S0|pin@30||45.5|47.5|sucDri10@0|inB|34.5|47.5
+Ametal-1|net@132|||S1800|pin@24||3.5|6|pin@28||45.5|6
+Ametal-1|net@133|||S2700|pin@28||45.5|6|pin@30||45.5|47.5
+Ametal-1|net@134|||S900|pin@24||3.5|6|pin@31||3.5|-40
+Ametal-1|net@136|||S1800|pin@31||3.5|-40|pin@32||9.5|-40
+Ametal-1|net@137|||S900|pin@32||9.5|-40|minusOne@0|fireLO[m1]|9.5|-56
+Ebit[1]||D5G5;|sucDri10@0|in[1]|I
+Ebit[2]||D5G5;|sucDri10@0|in[2]|I
+Ebit[3]||D5G5;|sucDri10@0|in[3]|I
+Ebit[4]||D5G5;|sucDri10@0|in[4]|I
+Ebit[5]||D5G5;|sucDri10@0|in[5]|I
+Ebit[6]||D5G5;|sucDri10@0|in[6]|I
+Efire[m1]||D5G4;|minusOne@0|fire[m1]|O
+Egnd||D5G4;|minusOne@0|gnd|G
+Egnd_1||D5G4;|minusOne@0|gnd_1|G
+Egnd_2||D5G5;|sucDri10@0|gnd_2|G
+Egnd_3||D5G5;|sucDri10@0|gnd_1|G
+EheadBit||D5G5;|sucDri10@0|inA|I
+Em1cate[1][F]||D5G5;|sucDri10@0|in[1]@451244315|I
+Em1cate[1][T]||D5G5;|sucDri10@0|m1cate[1][T]|O
+Em1cate[2][F]||D5G5;|sucDri10@0|in[2]@362228990|I
+Em1cate[2][T]||D5G5;|sucDri10@0|m1cate[2][T]|O
+Em1cate[3][F]||D5G5;|sucDri10@0|in[3]@341176303|I
+Em1cate[3][T]||D5G5;|sucDri10@0|m1cate[4][T]|O
+Em1cate[4][F]||D5G5;|sucDri10@0|in[4]@596770110|I
+Em1cate[4][T]||D5G5;|sucDri10@0|m1cate[6][T]|O
+Em1cate[5][F]||D5G5;|sucDri10@0|in[5]@689079609|I
+Em1cate[5][T]||D5G5;|sucDri10@0|m1cate[5][T]|O
+Em1cate[6][F]||D5G5;|sucDri10@0|in[6]@386420554|I
+Em1cate[6][T]||D5G5;|sucDri10@0|m1cate[3][T]|O
+Emc||D5G4;|minusOne@0|mc|I
+Emc_1||D5G4;|minusOne@0|mc_1|I
+Epred||D5G4;|minusOne@0|pred|I
+Es[1]||D5G4;|minusOne@0|s[1]|O
+Esucc[m1]||D5G4;|minusOne@0|succ[m1]|O
+Evdd||D5G4;|minusOne@0|vdd|P
+Evdd_2||D5G4;|minusOne@0|vdd_2|P
+Evdd_3||D5G4;|minusOne@0|vdd_3|P
+Evdd_4||D5G4;|minusOne@0|vdd_4|P
+Evdd_5||D5G5;|sucDri10@0|vdd_4|P
+Evdd_6||D5G5;|sucDri10@0|vdd_2|P
+Evdd_7||D5G5;|sucDri10@0|vdd_3|P
+Evdd_8||D5G5;|sucDri10@0|vdd_5|P
+X