migrate jelib->delib

[fleet.git] / chips / marina / electric / orangeTSMC090nm.delib / LEload.sch

diff --git a/chips/marina/electric/orangeTSMC090nm.delib/LEload.sch b/chips/marina/electric/orangeTSMC090nm.delib/LEload.sch
new file mode 100644 (file)
index 0000000..b239b17
--- /dev/null
+++ b/chips/marina/electric/orangeTSMC090nm.delib/LEload.sch
@@ -0,0 +1,13 @@
+HorangeTSMC090nm|8.10k
+
+# Cell LEload;1{sch}
+CLEload;1{sch}||schematic|1083965121000|1176245140811||ATTR_L(D5FLeave alone;G1;HNOLPUDX-20.5;Y-6.5;)S100|ATTR_LEWIRE(D5G1;HNPTX-20.5;Y-9.5;)I1|ATTR_layer(D5FLeave alone;G1;HNOLPX-20.5;Y-7.5;)S1|ATTR_width(D5FLeave alone;G1;HNOLPX-20.5;Y-8.5;)S3|prototype_center()I[0,0]
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NOff-Page|conn@0||-23|-1||||
+Ngeneric:Invisible-Pin|pin@0||-4|6|||||ART_message(BD5G2;)SLEload
+Ngeneric:Invisible-Pin|pin@3||-9|2|||||ART_message(D6G1;)S["wire in layer 'layer', 'L' lambda long,","'width' lambda wide, for the 180nm tech"]
+ILEload;1{ic}|wire180@0||12|6.63|||D0G4;|ATTR_L(D5G1;OLPUDX0.5;)S100|ATTR_LEWIRE(P)I1|ATTR_layer(D5G1;NOLPY-1;)S1|ATTR_width(D5G1;NOLPY-2;)S3
+ILEload_sub;1{ic}|wire@0||-10.5|-1|||D0G4;|ATTR_LEWIRECAP(D5G1;NOJTUDX0.5;Y-1.5;)S((@layer==0?15:@layer<6?25:30)+(@width-3))*1e-18*@L
+Awire|net@0|||0|wire@0|a|-14.5|-1|conn@0|y|-21|-1
+Ea||D4G2;|conn@0|a|B
+X