migrate jelib->delib

[fleet.git] / chips / marina / electric / orangeTSMC090nm.delib / NMOS4fwk_high.sch

diff --git a/chips/marina/electric/orangeTSMC090nm.delib/NMOS4fwk_high.sch b/chips/marina/electric/orangeTSMC090nm.delib/NMOS4fwk_high.sch
new file mode 100644 (file)
index 0000000..a1a9c86
--- /dev/null
+++ b/chips/marina/electric/orangeTSMC090nm.delib/NMOS4fwk_high.sch
@@ -0,0 +1,26 @@
+HorangeTSMC090nm|8.10k
+
+# Cell NMOS4fwk_high;1{sch}
+CNMOS4fwk_high;1{sch}||schematic|1021415734000|1159313323976||ATTR_Delay(D5G1;HNPX-8.5;Y-14.75;)I100|ATTR_L(D5FLeave alone;G1;HNOLPX-9;Y-13.5;)S2|ATTR_W(D5FLeave alone;G1;HNOLPX-8.5;Y-12.5;)S3|ATTR_CDL_template(D5G1;NTX1;Y-31.5;)SM$(node_name) $(d) $(g) $(s) $(b) nch_hvt W='$(W)*0.05u' L='$(L)*0.05u'|ATTR_NCC(D5G1;NTX0.5;Y-28.75;)StransistorType VTH-N-Transistor|ATTR_SPICE_template(D5G1;NTX4;Y-24;)SM$(node_name) $(d) $(g) $(s) $(b) nch_hvt W='$(W)*(1+ABN/sqrt($(W)*$(L)))' L='$(L)' DELVTO='AVT0N/sqrt($(W)*$(L))'|ATTR_SPICE_template_calibre(D5G1;NTX0.5;Y-34;)SM$(node_name) $(d) $(g) $(s) $(b) nch_hvt W='$(W)*0.05u' L='$(L)*0.05u'|ATTR_SPICE_template_smartspice(D5G1;NTY-21.5;)SM$(node_name) $(d) $(g) $(s) $(b) nch_hvt W='$(W)' L='$(L)'|ATTR_verilog_template(D5G1;NTX-1;Y-26.5;)Srtranif1 #($(Delay)) $(node_name) ($(d), $(s), $(g));|prototype_center()I[0,0]
+INMOS4fwk_high;1{ic}|NMOS4fwk@0||17|-1|||D0G4;|ATTR_Delay(D5G1;NPX3.5;Y-2;)I100|ATTR_L(D5G1;NOLPX3.5;)S2|ATTR_W(D6FLeave alone;G1;NOLPX2;Y1;)S3|ATTR_GEO(T)I0|ATTR_M(T)I1
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NOff-Page|conn@0||-10|-8||||
+NOff-Page|conn@1||4.5|0||||
+NOff-Page|conn@2||6|-16.5||||
+NOff-Page|conn@3||6|-9|||YRR|
+N4-Port-Transistor|nmos4p@0||-2|-8|||R||ATTR_length(D5FLeave alone;G1;OLX-1;Y1;)S"P(\"L\")"|ATTR_width(D5FLeave alone;G1.5;OLX0.5;Y-1;)S"P(\"W\")"|SIM_spice_model(D5G1;X1.5;Y-3;)Snch_hvt
+Ngeneric:Invisible-Pin|pin@0||0|11.5|||||ART_message(D5G6;)SNMOS4fwk_high
+NWire_Pin|pin@1||0|0||||
+NWire_Pin|pin@2||0|-16.5||||
+Ngeneric:Invisible-Pin|pin@3||1|5.5|||||ART_message(D5G2;)S4-terminal high-threshold weak NMOS device
+Awire|net@0|||900|pin@1||0|0|nmos4p@0|d|0|-6
+Awire|net@1|||1800|conn@0|y|-8|-8|nmos4p@0|g|-3|-8
+Awire|net@2|||1800|pin@1||0|0|conn@1|a|2.5|0
+Awire|net@3|||1800|pin@2||0|-16.5|conn@2|a|4|-16.5
+Awire|net@4|||900|nmos4p@0|s|0|-10|pin@2||0|-16.5
+Awire|net@5|||1800|nmos4p@0|b|0|-9|conn@3|y|4|-9
+Eb||D5G2;|conn@3|y|B
+Ed||D5G2;|conn@1|y|B
+Eg||D5G2;|conn@0|a|I
+Es||D5G2;|conn@2|y|B
+X