migrate jelib->delib

[fleet.git] / chips / marina / electric / orangeTSMC090nm.delib / gateResistor.sch

diff --git a/chips/marina/electric/orangeTSMC090nm.delib/gateResistor.sch b/chips/marina/electric/orangeTSMC090nm.delib/gateResistor.sch
new file mode 100644 (file)
index 0000000..50931b8
--- /dev/null
+++ b/chips/marina/electric/orangeTSMC090nm.delib/gateResistor.sch
@@ -0,0 +1,16 @@
+HorangeTSMC090nm|8.10k
+
+# Cell gateResistor;1{sch}
+CgateResistor;1{sch}||schematic|1047945706000|1158010267102||ATTR_W(D5G1;HNOLPX-13;Y-1;)S3|prototype_center()I[0,0]
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NOff-Page|conn@0||10|3||||
+NOff-Page|conn@1||-11.5|3||||
+IgateResistor;1{ic}|gateResi@0||18|10.5|||D0G4;|ATTR_W(D5G1;NOLPY-1.5;)S3
+Ngeneric:Invisible-Pin|pin@0||0|15.5|||||ART_message(D5G2;)S[models gate resistor in TSMC 180nm technology,where gate resistance is not felt to be important]
+Ngeneric:Invisible-Pin|pin@1||1.5|20.5|||||ART_message(D5G5;)S[gateResistor]
+NResistor|res@0||-0.5|3|||||SCHEM_resistance(D5G1;OL)S0.0010
+Awire|net@0|||1800|conn@1|y|-9.5|3|res@0|a|-2.5|3
+Awire|net@1|||0|conn@0|a|8|3|res@0|b|1.5|3
+Ein||D5G2;|conn@1|y|I
+Eout||D5G2;|conn@0|y|O
+X