migrate jelib->delib

[fleet.git] / chips / marina / electric / predicateM.delib / ohSRxor.sch

diff --git a/chips/marina/electric/predicateM.delib/ohSRxor.sch b/chips/marina/electric/predicateM.delib/ohSRxor.sch
new file mode 100644 (file)
index 0000000..edd6f3f
--- /dev/null
+++ b/chips/marina/electric/predicateM.delib/ohSRxor.sch
@@ -0,0 +1,70 @@
+HpredicateM|8.10k
+
+# External Libraries:
+
+LredFive|redFive
+
+# Cell ohSRxor;1{sch}
+CohSRxor;1{sch}||schematic|1231866290914|1240453549951|
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NOff-Page|conn@0||-29|0|||Y|
+NOff-Page|conn@1||0|-17|||YRRR|
+NOff-Page|conn@2||-15|18|||Y|
+NOff-Page|conn@3||25|0|||Y|
+IredFive:nms2b;1{ic}|nms2b@4||-12|-12|||D0G4;|ATTR_Delay(D5G1;NPX3;Y-0.5;)I100|ATTR_X(D5G1.5;NOJPX-2.25;Y1.5;)S5
+IredFive:nms2b;1{ic}|nms2b@5||12|-12|X||D0G4;|ATTR_Delay(D5G1;NPX3;Y-0.5;)I100|ATTR_X(D5G1.5;NOJPX-2.25;Y1.5;)S5
+IohSRxor;1{ic}|ohSRxor@1||36.5|32.5|||D5G4;
+NWire_Pin|pin@0||12|0||||
+NWire_Pin|pin@1||-12|0||||
+NWire_Pin|pin@2||0|0||||
+NWire_Pin|pin@3||-18|-12||||
+NWire_Pin|pin@4||-18|12||||
+NWire_Pin|pin@5||18|-12||||
+NWire_Pin|pin@6||18|12||||
+Ngeneric:Invisible-Pin|pin@7||0.5|29|||||ART_message(D5G3;)Sies 13 January 2009
+Ngeneric:Invisible-Pin|pin@8||0.5|33|||||ART_message(D5G4;)Sself-resetting mux
+Ngeneric:Invisible-Pin|pin@9||0.5|38|||||ART_message(D5G6;)SohSRxor
+NWire_Pin|pin@12||2|-8||||
+NWire_Pin|pin@13||2|-5||||
+NWire_Pin|pin@14||-2|-1||||
+NWire_Pin|pin@15||-2|8||||
+NWire_Pin|pin@16||-2|-8||||
+NWire_Pin|pin@17||-2|-5||||
+NWire_Pin|pin@18||2|-1||||
+NWire_Pin|pin@19||2|8||||
+NWire_Pin|pin@20||-2|-12||||
+Ngeneric:Invisible-Pin|pin@21||21.5|19|||||ART_message(D3G2;)S[output goes LO if:,"sel[1] & flag[T] or","sel[2] & flag[F] or",both.  HI otherwise.]
+IredFive:pms1;2{ic}|pms1@0||0|18|||D5G4;|ATTR_Delay(D5G1;NPX-2;Y0.25;)I100|ATTR_X(D5FLeave alone;G1.5;NOLPX3.25;Y2.75;)S5
+IredFive:pms2;1{ic}|pms2@0||-12|12|||D0G4;|ATTR_Delay(D5G1;NPX-3;Y-1.5;)I100|ATTR_X(D5G1.5;NOLPX2.25;Y1;)S1
+IredFive:pms2;1{ic}|pms2@1||12|12|X||D0G4;|ATTR_Delay(D5G1;NPX-3;Y-1.5;)I100|ATTR_X(D5G1.5;NOLPX2.25;Y1;)S1
+Awire|flag[F]|D5G2;Y-3.5;||2700|pin@5||18|-12|pin@6||18|12
+Awire|flag[T]|D5G2;||2700|pin@3||-18|-12|pin@4||-18|12
+Awire|net@0|||900|pin@1||-12|0|nms2b@4|d|-12|-6
+Awire|net@1|||900|pin@0||12|0|nms2b@5|d|12|-6
+Awire|net@2|||900|pms2@1|d|12|6|pin@0||12|0
+Awire|net@3|||900|pms2@0|d|-12|6|pin@1||-12|0
+Awire|net@4|||0|pin@2||0|0|pin@1||-12|0
+Awire|net@5|||0|pin@0||12|0|pin@2||0|0
+Awire|net@6|||900|pms1@0|d|0|16|pin@2||0|0|SIM_verilog_wire_type(D5G2;Y3;)Strireg
+Awire|net@8|||0|nms2b@4|g|-15|-12|pin@3||-18|-12
+Awire|net@10|||1800|pin@4||-18|12|pms2@0|g|-15|12
+Awire|net@11|||1800|nms2b@5|g|15|-12|pin@5||18|-12
+Awire|net@13|||0|pin@6||18|12|pms2@1|g|15|12
+Awire|net@17|||1800|pin@12||2|-8|nms2b@5|g2|9|-8
+Awire|net@19|||3150|pin@13||2|-5|pin@14||-2|-1
+Awire|net@20|||2700|pin@14||-2|-1|pin@15||-2|8
+Awire|net@22|||1800|nms2b@4|g2|-9|-8|pin@16||-2|-8
+Awire|net@23|||2700|pin@16||-2|-8|pin@17||-2|-5
+Awire|net@24|||2250|pin@17||-2|-5|pin@18||2|-1
+Awire|net@25|||2700|pin@18||2|-1|pin@19||2|8
+Awire|net@26|||1800|pin@19||2|8|pms2@1|g2|9|8
+Awire|net@31|||1800|pms2@0|g2|-9|8|pin@15||-2|8
+Awire|net@34|||0|pms1@0|g|-3|18|conn@2|y|-13|18
+Awire|net@37|||0|conn@3|a|23|0|pin@0||12|0
+Awire|sel[1]|D5G2;||900|pin@16||-2|-8|pin@20||-2|-12
+Awire|sel[2]|D5G2;||2700|pin@12||2|-8|pin@13||2|-5
+Eflag[T,F]||D4G2;|conn@0|a|I
+Eout||D6G2;|conn@3|y|O
+EresetLO||D4G2;|conn@2|a|I
+Esel[1,2]||D4G2;|conn@1|a|I
+X