migrate jelib->delib

[fleet.git] / chips / marina / electric / predicateM.delib / predSucDri.sch

diff --git a/chips/marina/electric/predicateM.delib/predSucDri.sch b/chips/marina/electric/predicateM.delib/predSucDri.sch
new file mode 100644 (file)
index 0000000..2bdab79
--- /dev/null
+++ b/chips/marina/electric/predicateM.delib/predSucDri.sch
@@ -0,0 +1,63 @@
+HpredicateM|8.10k
+
+# External Libraries:
+
+LdriversM|driversM
+
+LorangeTSMC090nm|orangeTSMC090nm
+
+LredFive|redFive
+
+# Cell predSucDri;1{sch}
+CpredSucDri;1{sch}||schematic|1232203758678|1232961207248|
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NOff-Page|conn@0||22.5|7||||
+NOff-Page|conn@1||-9.5|-5||||
+NOff-Page|conn@2||-10.5|1||||
+IredFive:nand2;1{ic}|na[1:5]|D5G3;Y5;|0.5|0|||D0G4;|ATTR_Delay(D5G1;NPX2.5;Y-3;)I100|ATTR_X(D5G1.5;NPX2.5;Y2.5;)S10|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1
+IpredSucDri;1{ic}|ohPredDo@1||30|26|||D5G4;
+Ngeneric:Invisible-Pin|pin@0||2.5|27|||||ART_message(D5G2;)Sthis is the do drivers
+Ngeneric:Invisible-Pin|pin@1||1.5|35.5|||||ART_message(D5G5;)SpredSucDri
+NBus_Pin|pin@2||-4|-1|-1|-1||
+Ngeneric:Invisible-Pin|pin@4||2|31.5|||||ART_message(D5G3;)Sies 17 January 2009
+NBus_Pin|pin@5||8|0|-1|-1||
+NBus_Pin|pin@6||8|7|-1|-1||
+NBus_Pin|pin@8||-4|-5|-1|-1||
+NWire_Pin|pin@9||-32|20||||
+NWire_Pin|pin@10||-32|23||||
+NWire_Pin|pin@11||-32|14||||
+NWire_Pin|pin@12||-32|17||||
+NWire_Pin|pin@13||-32|8||||
+NWire_Pin|pin@14||-32|11||||
+NWire_Pin|pin@15||-32|2||||
+NWire_Pin|pin@16||-32|5||||
+NWire_Pin|pin@17||-32|-4||||
+NWire_Pin|pin@18||-32|-1||||
+IdriversM:sucDri20plain;1{ic}|sd[1:5]|D5G3;Y-6;|14|7|Y||D5G4;
+IorangeTSMC090nm:wire90;1{ic}|wire90@0||-27|20|||D0G4;|ATTR_L(D5G1;PUD)D503.39999999999975|ATTR_LEWIRE(P)I1|ATTR_layer(D5G1;NPY-1;)I1|ATTR_width(D5G1;NPY-2;)I3
+IorangeTSMC090nm:wire90;1{ic}|wire90@1||-27|14|||D0G4;|ATTR_L(D5G1;PUD)D503.39999999999975|ATTR_LEWIRE(P)I1|ATTR_layer(D5G1;NPY-1;)I1|ATTR_width(D5G1;NPY-2;)I3
+IorangeTSMC090nm:wire90;1{ic}|wire90@2||-27|8|||D0G4;|ATTR_L(D5G1;PUD)D503.39999999999975|ATTR_LEWIRE(P)I1|ATTR_layer(D5G1;NPY-1;)I1|ATTR_width(D5G1;NPY-2;)I3
+IorangeTSMC090nm:wire90;1{ic}|wire90@3||-27|2|||D0G4;|ATTR_L(D5G1;PUD)D503.39999999999975|ATTR_LEWIRE(P)I1|ATTR_layer(D5G1;NPY-1;)I1|ATTR_width(D5G1;NPY-2;)I3
+IorangeTSMC090nm:wire90;1{ic}|wire90@4||-27|-4|||D0G4;|ATTR_L(D5G1;PUD)D503.39999999999975|ATTR_LEWIRE(P)I1|ATTR_layer(D5G1;NPY-1;)I1|ATTR_width(D5G1;NPY-2;)I3
+Abus|net@0||-0.5|IJ1800|pin@2||-4|-1|na[1:5]|ina|-2|-1
+Abus|net@1||-0.5|IJ1800|na[1:5]|out|3|0|pin@5||8|0
+Abus|net@2||-0.5|IJ1800|pin@6||8|7|sd[1:5]|in|12|7
+Abus|net@4||-0.5|IJ0|conn@0|a|20.5|7|sd[1:5]|succ|18|7
+Abus|net@6||-0.5|IJ1800|conn@1|y|-7.5|-5|pin@8||-4|-5
+Abus|net@7||-0.5|IJ2700|pin@8||-4|-5|pin@2||-4|-1
+Awire|net@8|||0|wire90@0|a|-29.5|20|pin@9||-32|20
+Awire|net@9|||0|wire90@1|a|-29.5|14|pin@11||-32|14
+Awire|net@10|||0|wire90@2|a|-29.5|8|pin@13||-32|8
+Awire|net@11|||0|wire90@3|a|-29.5|2|pin@15||-32|2
+Awire|net@12|||0|wire90@4|a|-29.5|-4|pin@17||-32|-4
+Awire|net@13|||1800|conn@2|y|-8.5|1|na[1:5]|inb|-2|1
+Abus|w[1:5]|D5G2;|-0.5|IJ2700|pin@5||8|0|pin@6||8|7
+Awire|w[1]|D5G2;||2700|pin@9||-32|20|pin@10||-32|23
+Awire|w[2]|D5G2;||2700|pin@11||-32|14|pin@12||-32|17
+Awire|w[3]|D5G2;||2700|pin@13||-32|8|pin@14||-32|11
+Awire|w[4]|D5G2;||2700|pin@15||-32|2|pin@16||-32|5
+Awire|w[5]|D5G2;||2700|pin@17||-32|-4|pin@18||-32|-1
+Edo[1:5]|do[Ld,Co,Mv,Tp,Lt]|D6G2;|conn@0|y|O
+Efire[pp]|fire[do]|D4G2;|conn@2|a|I
+Esel[1:5]|sel[Ld,Co,Mv,Tp,Lt]|D4G2;|conn@1|a|I
+X