migrate jelib->delib

[fleet.git] / chips / marina / electric / purpleFive.delib / LEsettings.sch

diff --git a/chips/marina/electric/purpleFive.delib/LEsettings.sch b/chips/marina/electric/purpleFive.delib/LEsettings.sch
new file mode 100644 (file)
index 0000000..7cad6ae
--- /dev/null
+++ b/chips/marina/electric/purpleFive.delib/LEsettings.sch
@@ -0,0 +1,15 @@
+HpurpleFive|8.10k
+
+# Cell LEsettings;1{sch}
+CLEsettings;1{sch}||schematic|1023920036000|1213471981644||ATTR_LESETTINGS(D6G1;HNPX-21;Y23;)I1|ATTR_alpha(D5G1;HNPX-18.5;Y25;)D0.7|ATTR_epsilon(D6G1;HNPX-21;Y28;)S0.01|ATTR_gate_cap(D6G1;HNPX-21;Y26;)F0.4|ATTR_keeper_ratio(D5G1;HNPX-17;Y24;)F0.1|ATTR_max_iter(D6G1;HNPX-21;Y27;)I40|ATTR_su(D6G1;HNPX-21;Y30;)S4.5|ATTR_wire_ratio(D6G1;HNPX-21;Y29;)S0.22|ATTR_SPICE_template(D5G1;NTX-7;Y9;)S**LEsettings: None needed for LEsettings|prototype_center()I[12000,48000]
+ILEsettings;1{ic}|LEsettin@2||-4|2|||D5G4;|ATTR_LESETTINGS(D6G1;NPX-4;Y-3.5;)I1|ATTR_alpha(D5G1;NPX-1.5;Y-1.5;)F0.7|ATTR_epsilon(D6G1;NPX-4;Y1.5;)F0.0010|ATTR_gate_cap(D6G1;NPX-4;Y-0.5;)F0.19|ATTR_keeper_ratio(D5G1;NPY-2.5;)F0.1|ATTR_max_iter(D6G1;NPX-4;Y0.5;)I30|ATTR_su(D6G1;NPX-4;Y3.5;)S3.7|ATTR_wire_ratio(D6G1;NPX-4;Y2.5;)F0.16
+Ngeneric:Facet-Center|art@0||0|0||||AV
+Ngeneric:Invisible-Pin|pin@0||-9.5|12|||||ART_message(D6G1;)S[this is the diffusion effort of PMOS gates (Cdiffp/Cgate)]
+Ngeneric:Invisible-Pin|pin@1||-9.5|13|||||ART_message(D6G1;)S[this is the diffusion effort of NMOS gates (Cdiffn/Cgate)]
+Ngeneric:Invisible-Pin|pin@2||-9.5|14|||||ART_message(D6G1;)S[gate cap. is used to convert cap loads to gate loads (fF/lambda)]
+Ngeneric:Invisible-Pin|pin@3||-9.5|15|||||ART_message(D6G1;)S[this sets the maximum number of iterations]
+Ngeneric:Invisible-Pin|pin@4||-9.5|16|||||ART_message(D6G1;)S[epsilon is the convergence criterion]
+Ngeneric:Invisible-Pin|pin@5||-9.5|17|||||ART_message(D6G1;)S[wire ratio is the default wire ratio: Cwire/Cgate]
+Ngeneric:Invisible-Pin|pin@6||-9.5|18|||||ART_message(D6G1;)S[su is the global step-up (fan-out)]
+Ngeneric:Invisible-Pin|pin@7||-24|21|||||ART_message(D6G2;)S[This Facet is used to set Logical Effort Settings]
+X