migrate jelib->delib

[fleet.git] / chips / marina / electric / purpleFive.delib / nand2LT.sch

diff --git a/chips/marina/electric/purpleFive.delib/nand2LT.sch b/chips/marina/electric/purpleFive.delib/nand2LT.sch
new file mode 100644 (file)
index 0000000..ea3ed75
--- /dev/null
+++ b/chips/marina/electric/purpleFive.delib/nand2LT.sch
@@ -0,0 +1,34 @@
+HpurpleFive|8.10k
+
+# External Libraries:
+
+LredFive|redFive
+
+# Cell nand2LT;1{sch}
+Cnand2LT;1{sch}||schematic|1021415734000|1159375693945||ATTR_Delay(D5G1;HNPX-17;Y-8.5;)I100|ATTR_LEGATE(D5G1;HNPTX-17;Y-13.5;)I1|ATTR_LEPARALLGRP(D5G1;HNPTX-17;Y-9.5;)I-1|ATTR_X(D5G1;HNOJPX-17;Y-7.5;)SLE.getdrive()|ATTR_drive0(D5G1;HNPTX-17;Y-11.5;)Sstrong0|ATTR_drive1(D5G1;HNPTX-17;Y-12.5;)Sstrong1|ATTR_su(D5G1;HNPTX-17.5;Y-10.5;)I-1|prototype_center()I[0,0]
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NOff-Page|conn@0||-14|-2.5||||
+NOff-Page|conn@1||-14|2.5||||
+NOff-Page|conn@2||14|0||||
+IredFive:nand2LT;1{ic}|nand2LT@0||0|0|||D0G4;|ATTR_Delay(D5G1;NOJPX2.5;Y-3;)S@Delay|ATTR_X(D5G1.5;NOJPX2.5;Y2.5;)S@X|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1
+Inand2LT;1{ic}|nand2LT@1||25|10.5|||D0G4;|ATTR_Delay(D5G1;NPX2.5;Y-3;)I100|ATTR_LEGATE(P)I1|ATTR_LEPARALLGRP(P)I-1|ATTR_X(D5G1.5;NOJPX2.5;Y2.5;)SLE.getdrive()|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1|ATTR_su(P)I-1
+NWire_Pin|pin@0||-6.5|-2.5||||
+NWire_Pin|pin@1||-6.5|-1||||
+NWire_Pin|pin@2||-6.5|1||||
+NWire_Pin|pin@3||-6.5|2.5||||
+Ngeneric:Invisible-Pin|pin@4||-1|16|||||ART_message(D5G2;)S[Sized assuming both inputs go low together]
+Ngeneric:Invisible-Pin|pin@5||22|-13|||||ART_message(D5G2;)S[X is drive strength,The pull-down is twice as strong as,one pull-up; or both pull-ups together,are as strong as the pull-down]
+Ngeneric:Invisible-Pin|pin@6||-1.5|18|||||ART_message(D5G2;)S[P to N width ratio is 1 to 2]
+Ngeneric:Invisible-Pin|pin@7||-2|25|||||ART_message(D5G6;)S[nand2LT]
+Ngeneric:Invisible-Pin|pin@8||-2|20|||||ART_message(D5G2;)S[LO-threshold NAND]
+Awire|net@0|||1800|pin@1||-6.5|-1|nand2LT@0|ina|-2.5|-1
+Awire|net@1|||1800|nand2LT@0|out|2.5|0|conn@2|a|12|0
+Awire|net@2|||0|nand2LT@0|inb|-2.5|1|pin@2||-6.5|1
+Awire|net@3|||900|pin@1||-6.5|-1|pin@0||-6.5|-2.5
+Awire|net@4|||0|pin@0||-6.5|-2.5|conn@0|y|-12|-2.5
+Awire|net@5|||2700|pin@2||-6.5|1|pin@3||-6.5|2.5
+Awire|net@6|||0|pin@3||-6.5|2.5|conn@1|y|-12|2.5
+Eina||D5G2;|conn@0|a|I|ATTR_le(D5G1;NY-1.5;)I1
+Einb||D5G2;|conn@1|a|I|ATTR_le(D5G1;NY2;)I1
+Eout||D5G2;|conn@2|y|O|ATTR_le(D5G1;NX-0.5;Y2;)F1.33
+X