migrate jelib->delib

[fleet.git] / chips / marina / electric / redFive.delib / inv2iCTLp.sch

diff --git a/chips/marina/electric/redFive.delib/inv2iCTLp.sch b/chips/marina/electric/redFive.delib/inv2iCTLp.sch
new file mode 100644 (file)
index 0000000..c964076
--- /dev/null
+++ b/chips/marina/electric/redFive.delib/inv2iCTLp.sch
@@ -0,0 +1,39 @@
+HredFive|8.10k
+
+# External Libraries:
+
+LorangeTSMC090nm|orangeTSMC090nm
+
+# Cell inv2iCTLp;1{sch}
+Cinv2iCTLp;1{sch}||schematic|993433994000|1158010267102||ATTR_X(D5G2;HNPX-19;Y-5;)I1|prototype_center()I[0,0]
+IorangeTSMC090nm:NMOSx;1{ic}|NMOS@0||0|0.5|||D0G4;|ATTR_Delay(D5G1;NPX3.5;Y-2;)I100|ATTR_X(D5G1.5;NOJPX3.5;Y0.5;)S@X
+IorangeTSMC090nm:PMOSx;1{ic}|PMOS@0||0|22|||D0G4;|ATTR_Delay(D5G1;NPX3.5;Y-2;)I175|ATTR_X(D5G1.5;NOJPX3.5;Y0.5;)S@X*2.0
+IorangeTSMC090nm:PMOSxwk;1{ic}|PMOSwk@0||0|15|||D0G4;|ATTR_Delay(D5G1;NPX3.5;Y-2;)I175|ATTR_X(D5G1.5;NOJPX3.5;Y0.5;)S@X*2.0
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NOff-Page|conn@0||12.5|8||||
+NOff-Page|conn@1||-12|0.5||||
+NOff-Page|conn@2||-11|15||||
+NOff-Page|conn@3||-11|22||||
+NGround|gnd@0||0|-6.5||||
+Iinv2iCTLp;1{ic}|inv2iCTL@0||15|27.75|||D0G4;|ATTR_X(D5G1.5;NPX1.5;Y2;)I2
+NWire_Pin|pin@0||0|8||||
+Ngeneric:Invisible-Pin|pin@1||0|33|||||ART_message(D5G3;)S[inv2iCTLp]
+NWire_Pin|pin@2||-2.5|22||||
+NWire_Pin|pin@3||0|20.5||||
+NPower|pwr@0||0|28||||
+Awire|net@0|||1800|pin@0||0|8|conn@0|a|10.5|8|SIM_verilog_wire_type(D5G1;)Strireg
+Awire|net@1|||2700|PMOS@0|d|0|20|pin@3||0|20.5
+Awire|net@2|||900|pwr@0||0|28|PMOS@0|s|0|24
+Awire|net@3|||1800|PMOS@0|g|-3|22|pin@2||-2.5|22
+Awire|net@4|||900|NMOS@0|s|0|-1.5|gnd@0||0|-4.5
+Awire|net@5|||900|pin@0||0|8|NMOS@0|d|0|2.5
+Awire|net@6|||900|PMOS@0|d|0|20|PMOSwk@0|s|0|17
+Awire|net@7|||2700|pin@0||0|8|PMOSwk@0|d|0|13
+Awire|net@8|||0|PMOSwk@0|g|-3|15|conn@2|y|-9|15
+Awire|net@9|||0|NMOS@0|g|-3|0.5|conn@1|y|-10|0.5
+Awire|net@10|||0|PMOS@0|g|-3|22|conn@3|y|-9|22
+Ectl||D5G2;X-4;|conn@2|y|I
+EinN||D5G2;|conn@1|a|I
+EinP||D4G2;|conn@3|a|I
+Eout||D5G2;|conn@0|y|O
+X