migrate jelib->delib

[fleet.git] / chips / marina / electric / registersM.delib / addr1in20Bx7.sch

diff --git a/chips/marina/electric/registersM.delib/addr1in20Bx7.sch b/chips/marina/electric/registersM.delib/addr1in20Bx7.sch
new file mode 100644 (file)
index 0000000..ac02603
--- /dev/null
+++ b/chips/marina/electric/registersM.delib/addr1in20Bx7.sch
@@ -0,0 +1,25 @@
+HregistersM|8.10k
+
+# External Libraries:
+
+LlatchesK|latchesK
+
+# Cell addr1in20Bx7;1{sch}
+Caddr1in20Bx7;1{sch}||schematic|1188688057760|1238334870912|I
+Iaddr1in20Bx7;1{ic}|addr1in2@0||17|11|||D5G4;
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NOff-Page|conn@0||-10|0||||
+NOff-Page|conn@1||10|0||||
+NOff-Page|conn@2||-2|-9|||R|
+IlatchesK:latch1in20B;1{ic}|lat[1:7]|D5G3;Y4;|0|0|||D5G4;
+Ngeneric:Invisible-Pin|pin@0||1.5|29|||||ART_message(D5G6;)Saddr1in20Bx7
+Ngeneric:Invisible-Pin|pin@1||0.5|20|||||ART_message(D5G3;)Sies 29 December 2008
+Ngeneric:Invisible-Pin|pin@2||-0.5|24|||||ART_message(D5G4;)SHI control address register
+Ngeneric:Invisible-Pin|pin@5||-29.5|13|||||ART_message(D6G3;)S[Bit arrangement:,01 02 03 04 05 06 07]
+Abus|net@2||-0.5|IJ1800|conn@0|y|-8|0|lat[1:7]|in[1]|-3|0
+Abus|net@3||-0.5|IJ1800|lat[1:7]|out[1]|3|0|conn@1|a|8|0
+Awire|net@6|||2700|conn@2|y|-2|-7|lat[1:7]|hcl|-2|-3
+Eain[1:7]||D4G2;|conn@0|a|I
+Eaout[1:7]||D6G2;|conn@1|y|O
+Efire||D4G2;|conn@2|a|I
+X