migrate jelib->delib

[fleet.git] / chips / marina / electric / registersM.delib / data1in20Bx37.sch

diff --git a/chips/marina/electric/registersM.delib/data1in20Bx37.sch b/chips/marina/electric/registersM.delib/data1in20Bx37.sch
new file mode 100644 (file)
index 0000000..f7a0c6b
--- /dev/null
+++ b/chips/marina/electric/registersM.delib/data1in20Bx37.sch
@@ -0,0 +1,62 @@
+HregistersM|8.10k
+
+# External Libraries:
+
+LlatchesK|latchesK
+
+LorangeTSMC090nm|orangeTSMC090nm
+
+# Cell data1in20Bx37;1{sch}
+Cdata1in20Bx37;1{sch}||schematic|1230593509808|1238334870912|I
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NOff-Page|conn@0||-2|-13|||R|
+NOff-Page|conn@1||-33|-7.5||||
+NOff-Page|conn@2||29.5|-7.5||||
+Idata1in20Bx37;1{ic}|data1in2@0||25.5|17|||D5G4;
+Iins1in20Bx18;1{ic}|ins1in20@0||-24|0|||D5G4;
+Iins1in20Bx18;1{ic}|ins1in20@1||24|0|||D5G4;
+IlatchesK:latch1in20B;1{ic}|latch1in@1||0|0|||D5G4;
+Ngeneric:Invisible-Pin|pin@0||2|43|||||ART_message(D5G6;)Sdata1in20Bx37
+Ngeneric:Invisible-Pin|pin@1||1|34|||||ART_message(D5G3;)Sies 21 February 2009
+Ngeneric:Invisible-Pin|pin@2||0|38|||||ART_message(D5G4;)Sa complete data register
+NBus_Pin|pin@5||31|0|-1|-1||
+NBus_Pin|pin@6||31|5.5|-1|-1||
+NBus_Pin|pin@8||-17|5|-1|-1||
+NBus_Pin|pin@9||-17|0|-1|-1||
+NBus_Pin|pin@10||-32|0|-1|-1||
+NBus_Pin|pin@12||16|0|-1|-1||
+NBus_Pin|pin@13||16|4.5|-1|-1||
+NBus_Pin|pin@15||-32|4.5|-1|-1||
+NWire_Pin|pin@16||-8|0||||
+NWire_Pin|pin@17||-8|4.5||||
+NWire_Pin|pin@18||8|0||||
+NWire_Pin|pin@19||8|4.5||||
+NWire_Pin|pin@20||-26|-7.5||||
+NWire_Pin|pin@21||22|-7.5||||
+NWire_Pin|pin@23||-2|-7.5||||
+IorangeTSMC090nm:wire90;1{ic}|wire90@2||-12.5|-7.5|X||D0G4;|ATTR_L(D5G1;PUD)S2550|ATTR_LEWIRE(P)I1|ATTR_layer(D5G1;NPY-1;)I1|ATTR_width(D5G1;NPY-2;)I3
+IorangeTSMC090nm:wire90;1{ic}|wire90@3||11|-7.5|X||D0G4;|ATTR_L(D5G1;PUD)S2550|ATTR_LEWIRE(P)I1|ATTR_layer(D5G1;NPY-1;)I1|ATTR_width(D5G1;NPY-2;)I3
+Abus|in[1:18]|D5G2;|-0.5|IJ2700|pin@12||16|0|pin@13||16|4.5
+Awire|in[19]|D5G2;||2700|pin@16||-8|0|pin@17||-8|4.5
+Abus|in[20:37]|D5G2;|-0.5|IJ900|pin@15||-32|4.5|pin@10||-32|0
+Abus|net@2||-0.5|IJ1800|ins1in20@1|out[1:18]|27|0|pin@5||31|0
+Abus|net@5||-0.5|IJ0|pin@9||-17|0|ins1in20@0|out[1:18]|-21|0
+Abus|net@6||-0.5|IJ0|ins1in20@0|in[1:18]|-27|0|pin@10||-32|0
+Abus|net@8||-0.5|IJ0|ins1in20@1|in[1:18]|21|0|pin@12||16|0
+Awire|net@13|||0|latch1in@1|in[1]|-3|0|pin@16||-8|0
+Awire|net@15|||1800|latch1in@1|out[1]|3|0|pin@18||8|0
+Awire|net@17|||900|ins1in20@0|hcl[1]|-26|-3|pin@20||-26|-7.5
+Awire|net@19|||2700|pin@21||22|-7.5|ins1in20@1|hcl[1]|22|-3
+Awire|net@23|||900|latch1in@1|hcl|-2|-3|pin@23||-2|-7.5
+Awire|net@24|||1800|pin@20||-26|-7.5|wire90@2|b|-15|-7.5
+Awire|net@25|||900|pin@23||-2|-7.5|conn@0|y|-2|-11
+Awire|net@26|||1800|wire90@2|a|-10|-7.5|pin@23||-2|-7.5
+Awire|net@27|||1800|pin@23||-2|-7.5|wire90@3|b|8.5|-7.5
+Awire|net@28|||1800|wire90@3|a|13.5|-7.5|pin@21||22|-7.5
+Abus|out[1:18]|D5G2;|-0.5|IJ2700|pin@5||31|0|pin@6||31|5.5
+Awire|out[19]|D5G2;||2700|pin@18||8|0|pin@19||8|4.5
+Abus|out[20:37]|D5G2;|-0.5|IJ2700|pin@9||-17|0|pin@8||-17|5
+Ein[1:37]||D4G2;|conn@1|a|I
+Eout[1:37]||D6G2;|conn@2|y|O
+Etake||D4G2;|conn@0|a|I
+X