migrate jelib->delib

[fleet.git] / chips / marina / electric / registersM.delib / newDregister.sch

diff --git a/chips/marina/electric/registersM.delib/newDregister.sch b/chips/marina/electric/registersM.delib/newDregister.sch
new file mode 100644 (file)
index 0000000..eebb49e
--- /dev/null
+++ b/chips/marina/electric/registersM.delib/newDregister.sch
@@ -0,0 +1,61 @@
+HregistersM|8.10k
+
+# External Libraries:
+
+LorangeTSMC090nm|orangeTSMC090nm
+
+LredFive|redFive
+
+# Cell newDregister;1{sch}
+CnewDregister;1{sch}||schematic|1233568232067|1238334870912|I
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NOff-Page|conn@0||13.5|5.5||||
+NOff-Page|conn@1||-8.5|-0.5||||
+NOff-Page|conn@2||-14|14.5|||XRR|
+NOff-Page|conn@3||2.5|-3|||YRRR|
+Idata2in60Cx37;1{ic}|data2in6@0||4.5|5.5|||D5G4;
+IredFive:inv;1{ic}|inv@0||14.5|-10|X||D0G4;|ATTR_Delay(D5G1;NPX2;Y-2;)I100|ATTR_X(D5G1.5;NPX1.5;Y2;)S40|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1
+InewDregister;1{ic}|newDregi@0||32.5|22|||D5G4;
+Ngeneric:Invisible-Pin|pin@0||-1.5|33.5|||||ART_message(D5G6;)SnewDregister
+Ngeneric:Invisible-Pin|pin@1||-1.5|23.5|||||ART_message(D5G3;)Sies 15 February 2009
+Ngeneric:Invisible-Pin|pin@2||-1.5|28.5|||||ART_message(D5G3;)SD register with linear in and out pins
+NBus_Pin|pin@3||-4|-0.5|-1|-1||
+NBus_Pin|pin@4||-4|4.5|-1|-1||
+NBus_Pin|pin@6||-4|6.5|-1|-1||
+NBus_Pin|pin@7||-4|12.5|-1|-1||
+NBus_Pin|pin@8||-6.5|-14.5|-1|-1|X|
+Ngeneric:Invisible-Pin|pin@12||22|-15|||||ART_message(D3G2;)S[This shadow register,copies 18 bits of the,"output when not take[B]."]
+NBus_Pin|pin@14||12|-18|-1|-1|X|
+NBus_Pin|pin@15||12|-21.5|-1|-1|X|
+NBus_Pin|pin@16||-6.5|-19|-1|-1|X|
+NWire_Pin|pin@31||19|-10|||X|
+NWire_Pin|pin@32||19|-3|||X|
+NBus_Pin|pin@43||12|-16|-1|-1||
+NBus_Pin|pin@44||12|-12.5|-1|-1||
+NWire_Pin|pin@45||6|-10||||
+Ngeneric:Invisible-Pin|pin@53||-39.5|8|||||ART_message(D3G2;)S["dp[1:37,B] = data predecessor","and its bonus bit, B","ps[1:20] = predicate stage"]
+Ishadow;1{ic}|shadow@0||3|-17|X||D5G4;
+IorangeTSMC090nm:wire90;1{ic}|wire90@0||1|-10|X||D0G4;|ATTR_L(D5G1;PUD)D4175.400000000001|ATTR_LEWIRE(P)I1|ATTR_layer(D5G1;NPY-1;)I1|ATTR_width(D5G1;NPY-2;)I3
+Abus|net@0||-0.5|IJ1800|data2in6@0|aout[1:14,TT]|7.5|5.5|conn@0|a|11.5|5.5
+Abus|net@1||-0.5|IJ1800|conn@1|y|-6.5|-0.5|pin@3||-4|-0.5
+Abus|net@2||-0.5|IJ2700|pin@3||-4|-0.5|pin@4||-4|4.5
+Abus|net@3||-0.5|IJ900|data2in6@0|fire[A,B]|2.5|2.5|conn@3|y|2.5|-1
+Abus|net@4||-0.5|IJ1800|pin@4||-4|4.5|data2in6@0|ainA[1:14,TT]|1.5|4.5
+Abus|net@5||-0.5|IJ1800|pin@6||-4|6.5|data2in6@0|ainB[1:14,TT]|1.5|6.5
+Abus|net@10||-0.5|IJ1800|shadow@0|in[1:18]|7|-18|pin@14||12|-18
+Abus|net@11||-0.5|IJ0|shadow@0|out[1:18]|-2|-19|pin@16||-6.5|-19
+Awire|net@38|||1800|inv@0|in|17|-10|pin@31||19|-10
+Abus|net@63||-0.5|IJ1800|shadow@0|inn[19:36]|7|-16|pin@43||12|-16
+Awire|net@66|||900|pin@45||6|-10|shadow@0|hcl|6|-14
+Awire|net@68|||0|inv@0|out|12|-10|pin@45||6|-10
+Awire|net@69|||0|pin@45||6|-10|wire90@0|a|3.5|-10
+Abus|out[1:18]|D5G2;|-0.5|IJ900|pin@14||12|-18|pin@15||12|-21.5
+Abus|ps[1:15],ss[16:37]|D5G2;|-0.5|IJ2700|pin@6||-4|6.5|pin@7||-4|12.5
+Abus|ps[15:20]|D5G2;|-0.5|IJ2700|pin@43||12|-16|pin@44||12|-12.5
+Abus|ss[16:37]|D5G2;|-0.5|IJ2700|pin@16||-6.5|-19|pin@8||-6.5|-14.5
+Awire|take[B]|D5G2;||2700|pin@31||19|-10|pin@32||19|-3
+EinA[1:37]|dp[1:37]|D4G2;|conn@1|a|I
+Eout[1:37]||D6G2;|conn@0|y|O
+EinB[1:20]|ps[1:20]|D4G2;|conn@2|a|I
+Etake[A,B]||D4G2;|conn@3|a|I
+X