migrate jelib->delib

[fleet.git] / chips / marina / electric / registersM.delib / newPathReg.sch

diff --git a/chips/marina/electric/registersM.delib/newPathReg.sch b/chips/marina/electric/registersM.delib/newPathReg.sch
new file mode 100644 (file)
index 0000000..c13dd6a
--- /dev/null
+++ b/chips/marina/electric/registersM.delib/newPathReg.sch
@@ -0,0 +1,106 @@
+HregistersM|8.10k
+
+# External Libraries:
+
+LdriversM|driversM
+
+LorangeTSMC090nm|orangeTSMC090nm
+
+LredFive|redFive
+
+LwiresL|wiresL
+
+# Cell newPathReg;1{sch}
+CnewPathReg;1{sch}||schematic|1233579614045|1241194990220|
+Iaddr2in60Cx15;1{ic}|addr2in6@0||0|0|||D5G4;
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NOff-Page|conn@0||12|0||||
+NOff-Page|conn@1||-28|-7||||
+NOff-Page|conn@3||-31|3|||XRR|
+NOff-Page|conn@4||-27|-17|||XRR|
+IredFive:inv;1{ic}|inv@1||-32|-24|||D0G4;|ATTR_Delay(D5G1;NPX2;Y-2;)I100|ATTR_X(D5FLeave alone;G1.5;NPX1.5;Y2;)S10|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1
+IredFive:inv;1{ic}|inv@2||-32|-31|||D0G4;|ATTR_Delay(D5G1;NPX2;Y-2;)I100|ATTR_X(D5FLeave alone;G1.5;NPX1.5;Y2;)S10|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1
+IredFive:inv;1{ic}|inv@3||-29|8|||D0G4;|ATTR_Delay(D5G1;NPX1;Y-3;)I100|ATTR_X(D5FLeave alone;G1.5;NPX1.5;Y2;)S10|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1
+IredFive:invI;2{ic}|invI@0||1.5|-26|||D0G4;|ATTR_Delay(D5G1;NPX8;Y-2;)I100|ATTR_X(D5FLeave alone;G1.5;NPX1.5;Y2;)S30|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1
+IdriversM:latchAndDriver30;1{ic}|latchAnd@1||-10|-16|Y||D5G4;
+IredFive:nand3;1{ic}|nand3@1||-12|-26|||D0G4;|ATTR_Delay(D5G1;NPX4;Y-2.5;)I100|ATTR_X(D5G1.5;NPX3;Y2.5;)S6.667|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1
+InewPathReg;1{ic}|newPathR@0||22|10|||D5G4;
+Ngeneric:Invisible-Pin|pin@0||0.5|25.5|||||ART_message(D5G6;)SnewPathRegister
+Ngeneric:Invisible-Pin|pin@1||-0.5|14.5|||||ART_message(D5G3;)S[ies 2 February 2009,revised 11 April 2009]
+Ngeneric:Invisible-Pin|pin@2||-1.5|20.5|||||ART_message(D5G4;)SThis is the path register
+NBus_Pin|pin@4||-15|-5|-1|-1||
+NBus_Pin|pin@5||-15|-1|-1|-1||
+NBus_Pin|pin@6||-6|6|-1|-1||
+NBus_Pin|pin@7||-6|1|-1|-1||
+NBus_Pin|pin@8||-2|-6.5|-1|-1||
+NWire_Pin|pin@9||6.5|-16||||
+NWire_Pin|pin@10||6.5|-12.5||||
+NWire_Pin|pin@11||17.5|-26||||
+NWire_Pin|pin@12||17.5|-22.5||||
+NWire_Pin|pin@14||-18|-17||||
+NWire_Pin|pin@16||-39.5|-20.5||||
+NWire_Pin|pin@18||-18|-24||||
+NWire_Pin|pin@19||-20|-31||||
+NWire_Pin|pin@20||-20|-28||||
+NWire_Pin|pin@21||-20|-24||||
+NWire_Pin|pin@22||-20|-26||||
+NWire_Pin|pin@25||-39.5|-24||||
+NWire_Pin|pin@26||-39.5|-27.5||||
+NWire_Pin|pin@28||-39.5|-31||||
+NWire_Pin|pin@29||-18|-15||||
+NWire_Pin|pin@30||-18|-12.5||||
+Ngeneric:Invisible-Pin|pin@31||13.5|-13.5|||||ART_message(D3G2;)S[March 24 fix:,"take[ps] acts if ps[14] is one,","take[dp] acts if ps[13,14] both zero",register wiring is OK.]
+NWire_Pin|pin@32||-34|8||||
+NWire_Pin|pin@33||-34|5||||
+NWire_Pin|pin@34||-12|8||||
+NWire_Pin|pin@35||-12|5||||
+Ngeneric:Invisible-Pin|pin@36||-43.5|19.5|||||ART_message(D3G2;)S[April 11 fix:,"ps[15] needs inversion",before entering the path,register.]
+IwiresL:tranCap;1{ic}|tc[1:2]|D5G3;Y4;|-46|6|||D5G4;
+IorangeTSMC090nm:wire90;1{ic}|wire90@0||0|-16|||D0G4;|ATTR_L(D5FLeave alone;G1;PUD)D3495.7000000000016|ATTR_LEWIRE(P)I1|ATTR_layer(D5FLeave alone;G1;NPY-1;)I1|ATTR_width(D5FLeave alone;G1;NPY-2;)I3
+IorangeTSMC090nm:wire90;1{ic}|wire90@1||10|-26|||D0G4;|ATTR_L(D5FLeave alone;G1;PUD)D3616.3000000000015|ATTR_LEWIRE(P)I1|ATTR_layer(D5FLeave alone;G1;NPY-1;)I1|ATTR_width(D5FLeave alone;G1;NPY-2;)I3
+IorangeTSMC090nm:wire90;1{ic}|wire90@3||-24.5|-24|||D0G4;|ATTR_L(D5FLeave alone;G1;PUD)D270.0|ATTR_LEWIRE(P)I1|ATTR_layer(D5FLeave alone;G1;NPY-1;)I1|ATTR_width(D5FLeave alone;G1;NPY-2;)I3
+IorangeTSMC090nm:wire90;1{ic}|wire90@4||-24.5|-31|||D0G4;|ATTR_L(D5FLeave alone;G1;PUD)D358.0|ATTR_LEWIRE(P)I1|ATTR_layer(D5FLeave alone;G1;NPY-1;)I1|ATTR_width(D5FLeave alone;G1;NPY-2;)I3
+IorangeTSMC090nm:wire90;1{ic}|wire90@5||-21.5|8|||D0G4;|ATTR_L(D5FLeave alone;G1;PUD)D433.39999999999986|ATTR_LEWIRE(P)I1|ATTR_layer(D5FLeave alone;G1;NPY-1;)I1|ATTR_width(D5FLeave alone;G1;NPY-2;)I3
+IorangeTSMC090nm:wire90;1{ic}|wire90@6||-5|-26|||D0G4;|ATTR_L(D5FLeave alone;G1;PUD)D425.5999999999999|ATTR_LEWIRE(P)I1|ATTR_layer(D5FLeave alone;G1;NPY-1;)I1|ATTR_width(D5FLeave alone;G1;NPY-2;)I3
+Abus|net@4||-0.5|IJ1800|pin@5||-15|-1|addr2in6@0|inA[1:37]|-3|-1
+Abus|net@7||-0.5|IJ1800|pin@7||-6|1|addr2in6@0|inB[1:37]|-3|1
+Abus|net@11||-0.5|IJ0|conn@0|a|10|0|addr2in6@0|out[1:37]|3|0
+Awire|net@18|||0|latchAnd@1|inB|-14|-17|pin@14||-18|-17
+Awire|net@25|||2700|pin@19||-20|-31|pin@20||-20|-28
+Awire|net@28|||900|pin@21||-20|-24|pin@22||-20|-26
+Awire|net@31|||1800|pin@25||-39.5|-24|inv@1|in|-34.5|-24
+Awire|net@33|||1800|pin@28||-39.5|-31|inv@2|in|-34.5|-31
+Awire|net@36|||0|latchAnd@1|inA|-14|-15|pin@29||-18|-15
+Awire|net@38|||0|pin@14||-18|-17|conn@4|y|-25|-17
+Awire|net@39|||900|pin@14||-18|-17|pin@18||-18|-24
+Awire|net@40|||1800|invI@0|out|4|-26|wire90@1|a|7.5|-26
+Awire|net@41|||1800|wire90@1|b|12.5|-26|pin@11||17.5|-26
+Awire|net@42|||0|pin@9||6.5|-16|wire90@0|b|2.5|-16
+Awire|net@43|||0|wire90@0|a|-2.5|-16|latchAnd@1|out|-6|-16
+Awire|net@44|||1800|wire90@4|b|-22|-31|pin@19||-20|-31
+Awire|net@45|||0|pin@21||-20|-24|wire90@3|b|-22|-24
+Awire|net@46|||0|wire90@3|a|-27|-24|inv@1|out|-29.5|-24
+Awire|net@47|||1800|inv@2|out|-29.5|-31|wire90@4|a|-27|-31
+Awire|net@48|||0|inv@3|in|-31.5|8|pin@32||-34|8
+Awire|net@52|||0|wire90@5|a|-24|8|inv@3|out|-26.5|8
+Awire|net@53|||1800|wire90@5|b|-19|8|pin@34||-12|8
+Awire|net@55|||0|nand3@1|inc|-14.5|-24|pin@18||-18|-24
+Awire|net@56|||1800|pin@22||-20|-26|nand3@1|inb|-14.5|-26
+Awire|net@57|||1800|pin@20||-20|-28|nand3@1|ina|-14.5|-28
+Awire|net@58|||1800|wire90@6|b|-2.5|-26|invI@0|in|-1|-26
+Awire|net@59|||0|wire90@6|a|-7.5|-26|nand3@1|out|-9.5|-26
+Awire|ps[13]|D5G2;||2700|pin@25||-39.5|-24|pin@16||-39.5|-20.5
+Awire|ps[14]|D5G2;||2700|pin@28||-39.5|-31|pin@26||-39.5|-27.5
+Awire|ps[14]|D5G2;||2700|pin@29||-18|-15|pin@30||-18|-12.5
+Awire|ps[15]|D5G2;||900|pin@32||-34|8|pin@33||-34|5
+Abus|ps[15not,1:13,13]|D5G2;|-0.5|IJ900|pin@6||-6|6|pin@7||-6|1
+Awire|ps[15not]|D5G2;||900|pin@34||-12|8|pin@35||-12|5
+Abus|ps[15not],dp[1:12,12,12]|D5G2;|-0.5|IJ2700|pin@4||-15|-5|pin@5||-15|-1
+Abus|take[dp,ps]|D5G2;|-0.5|IJ900|addr2in6@0|take[A,B]|-2|-3|pin@8||-2|-6.5
+Awire|take[dp]|D5G2;||2700|pin@11||17.5|-26|pin@12||17.5|-22.5
+Awire|take[ps]|D5G2;||2700|pin@9||6.5|-16|pin@10||6.5|-12.5
+Eaout[1:14,TT]|aout[TT,1:14]|D6G2;|conn@0|y|O
+EainA[1:14,TT]|dp[1:12]|D4G2;|conn@1|a|I
+Eps[16:30]|fire[M]|D4G2;|conn@4|a|I
+EainB[1:14,TT]|ps[1:15]|D4G2;|conn@3|a|I
+X