migrate jelib->delib

[fleet.git] / chips / marina / electric / registersM.delib / shadow.sch

diff --git a/chips/marina/electric/registersM.delib/shadow.sch b/chips/marina/electric/registersM.delib/shadow.sch
new file mode 100644 (file)
index 0000000..3118967
--- /dev/null
+++ b/chips/marina/electric/registersM.delib/shadow.sch
@@ -0,0 +1,113 @@
+HregistersM|8.10k
+
+# External Libraries:
+
+LlatchGroupsK|latchGroupsK
+
+LorangeTSMC090nm|orangeTSMC090nm
+
+# Cell shadow;4{sch}
+Cshadow;4{sch}||schematic|1233348164824|1238334870912|I
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NOff-Page|conn@0||-13.5|9||||
+NOff-Page|conn@1||0|10|||RRR|
+NOff-Page|conn@3||14|9||||
+NOff-Page|conn@6||-13.5|13||||
+IlatchGroupsK:dataMux;1{ic}|dl[1:9]|D5G3;X10;Y4;|-12|0|X||D5G4;
+IlatchGroupsK:dataMux;1{ic}|dr[1:9]|D5G3;X10;Y4;|12|0|||D5G4;
+Ngeneric:Invisible-Pin|pin@0||0|30.5|||||ART_message(D5G6;)Sshadow
+Ngeneric:Invisible-Pin|pin@1||0|20.5|||||ART_message(D5G3;)Sies 28 March 2009
+Ngeneric:Invisible-Pin|pin@2||0|25.5|||||ART_message(D5G3;)Sthe shadow register
+NBus_Pin|pin@4||15|6|-1|-1||
+NBus_Pin|pin@6||-15|6|-1|-1||
+NWire_Pin|pin@7||9|4||||
+NWire_Pin|pin@9||-9|4||||
+NWire_Pin|pin@10||0|4||||
+NBus_Pin|pin@12||-4|0|-1|-1||
+NBus_Pin|pin@13||-4|-3|-1|-1||
+NBus_Pin|pin@15||3|0|-1|-1||
+NBus_Pin|pin@16||3|3|-1|-1||
+NBus_Pin|pin@17||23|-2|-1|-1||
+NBus_Pin|pin@18||23|-6|-1|-1||
+NBus_Pin|pin@19||-21|-2|-1|-1||
+NBus_Pin|pin@20||-21|-6|-1|-1||
+Ngeneric:Invisible-Pin|pin@21||-20|-14.5|||||ART_message(D3G2;)S["in layout,",the left side does,low order bits.]
+Ngeneric:Invisible-Pin|pin@22||9.5|-13.5|||||ART_message(D3G2;)S["in layout,",the right side does,high order bits.,N.B. reverse order,"dr[1:9] vs inn[18:10]"]
+NBus_Pin|pin@24||46|-2|-1|-1||
+NBus_Pin|pin@25||46|-8|-1|-1||
+NBus_Pin|pin@26||39|6|-1|-1||
+NWire_Pin|pin@27||12|-4||||
+NWire_Pin|pin@28||12|-7||||
+NWire_Pin|pin@29||36|-7||||
+NWire_Pin|pin@30||36|-4||||
+NWire_Pin|pin@31||-12|-7||||
+NWire_Pin|pin@32||-12|-4||||
+NBus_Pin|pin@34||31|0|-1|-1||
+NBus_Pin|pin@35||31|-3|-1|-1||
+NBus_Pin|pin@36||-30|6|-1|-1||
+NBus_Pin|pin@37||-30|1|-1|-1||
+NWire_Pin|pin@39||-30|-1||||
+NBus_Pin|pin@40||-43|0|-1|-1||
+NBus_Pin|pin@41||-43|5|-1|-1||
+NWire_Pin|pin@42||-36|18||||
+NWire_Pin|pin@43||-36|22.5||||
+NWire_Pin|pin@44||-36|24||||
+NWire_Pin|pin@45||-36|28.5||||
+NWire_Pin|pin@47||-30|-10||||
+NWire_Pin|pin@48||-30|-7||||
+Ngeneric:Invisible-Pin|pin@52||-6|-9|||||ART_message(D3G2;)S["inn[1:6] are 6 D register",outputs centered to,drive the counter mux]
+Ishadow;1{ic}|shadow@0||30|21|||D5G4;
+IshadowMux4;1{ic}|shadowMu@1||36|0|||D5G4;
+IsignLogic;1{ic}|signLogi@0||-36|0|Y||D5G4;
+IorangeTSMC090nm:wire90;1{ic}|wire90@1||-30|18|||D0G4;|ATTR_L(D5G1;PUD)D4861.700000000003|ATTR_LEWIRE(P)I1|ATTR_layer(D5G1;NPY-1;)I1|ATTR_width(D5G1;NPY-2;)I3
+IorangeTSMC090nm:wire90;1{ic}|wire90@2||-30|24|||D0G4;|ATTR_L(D5G1;PUD)D5555.800000000003|ATTR_LEWIRE(P)I1|ATTR_layer(D5G1;NPY-1;)I1|ATTR_width(D5G1;NPY-2;)I3
+IorangeTSMC090nm:wire90;1{ic}|wire90@3||-25.5|-10|||D0G4;|ATTR_L(D5G1;PUD)D5262.900000000003|ATTR_LEWIRE(P)I1|ATTR_layer(D5G1;NPY-1;)I1|ATTR_width(D5G1;NPY-2;)I3
+Abus|inB[15,20]|D5G2;|-0.5|IJ2700|pin@40||-43|0|pin@41||-43|5
+Abus|inB[16:19]|D5G2;|-0.5|IJ900|pin@34||31|0|pin@35||31|-3
+Abus|inn[1:9]|D5G2;|-0.5|IJ900|pin@12||-4|0|pin@13||-4|-3
+Abus|inn[18:10]|D5G2;|-0.5|IJ2700|pin@15||3|0|pin@16||3|3
+Abus|net@9||-0.5|IJ900|pin@4||15|6|dr[1:9]|s[T,F]|15|1
+Abus|net@16||-0.5|IJ900|pin@6||-15|6|dl[1:9]|s[T,F]|-15|1
+Awire|net@17|||900|pin@7||9|4|dr[1:9]|hcl|9|3
+Awire|net@18|||0|pin@7||9|4|pin@10||0|4
+Awire|net@20|||900|pin@9||-9|4|dl[1:9]|hcl|-9|3
+Awire|net@22|||900|conn@1|y|0|8|pin@10||0|4
+Abus|net@26||-0.5|IJ1800|dl[1:9]|in[1]|-8|0|pin@12||-4|0
+Abus|net@29||-0.5|IJ0|dr[1:9]|in[1]|8|0|pin@15||3|0
+Abus|net@32||-0.5|IJ1800|dr[1:9]|out[1]|17|-2|pin@17||23|-2
+Abus|net@34||-0.5|IJ0|dl[1:9]|out[1]|-17|-2|pin@19||-21|-2
+Awire|net@39|||1800|pin@9||-9|4|pin@10||0|4
+Abus|net@40||-0.5|IJ1800|shadowMu@1|out[16:19]|41|-2|pin@24||46|-2
+Abus|net@42||-0.5|IJ1800|pin@4||15|6|pin@26||39|6
+Abus|net@43||-0.5|IJ900|pin@26||39|6|shadowMu@1|s[T,F]|39|1
+Awire|net@44|||1800|pin@27||12|-4|dr[1:9]|inB[1]|13|-4
+Awire|net@45|||900|pin@27||12|-4|pin@28||12|-7
+Awire|net@46|||1800|pin@28||12|-7|pin@29||36|-7
+Awire|net@47|||2700|pin@29||36|-7|pin@30||36|-4
+Awire|net@48|||1800|pin@30||36|-4|shadowMu@1|sign|37|-4
+Awire|net@51|||2700|pin@31||-12|-7|pin@32||-12|-4
+Awire|net@52|||0|pin@32||-12|-4|dl[1:9]|inB[1]|-13|-4
+Abus|net@55||-0.5|IJ0|shadowMu@1|lit[16:19]|35|0|pin@34||31|0
+Abus|net@57||-0.5|IJ0|pin@6||-15|6|pin@36||-30|6
+Abus|net@59||-0.5|IJ0|pin@37||-30|1|signLogi@0|s[T,F]|-34|1
+Awire|net@62|||0|pin@39||-30|-1|signLogi@0|sign|-34|-1
+Abus|net@63||-0.5|IJ0|signLogi@0|inB[15,20]|-39|0|pin@40||-43|0
+Abus|net@65||-0.5|IJ0|pin@4||15|6|pin@6||-15|6
+Awire|net@69|||0|wire90@1|a|-32.5|18|pin@42||-36|18
+Awire|net@71|||0|wire90@2|a|-32.5|24|pin@44||-36|24
+Awire|net@73|||0|wire90@3|a|-28|-10|pin@47||-30|-10
+Awire|net@76|||2700|pin@47||-30|-10|pin@48||-30|-7
+Awire|net@77|||0|pin@31||-12|-7|pin@48||-30|-7
+Awire|net@80|||0|pin@28||12|-7|pin@31||-12|-7
+Abus|outt[16:19]|D5G2;|-0.5|IJ900|pin@24||46|-2|pin@25||46|-8
+Abus|outt[20:28]|D5G2;|-0.5|IJ900|pin@19||-21|-2|pin@20||-21|-6
+Abus|outt[37:29]|D5G2;|-0.5|IJ900|pin@17||23|-2|pin@18||23|-6
+Awire|s[F]|D5G2;||2700|pin@42||-36|18|pin@43||-36|22.5
+Abus|s[T,F]|D5G2;|-0.5|IJ900|pin@36||-30|6|pin@37||-30|1
+Awire|s[T]|D5G2;||2700|pin@44||-36|24|pin@45||-36|28.5
+Awire|sign|D5G2;||2700|pin@48||-30|-7|pin@39||-30|-1
+Ehcl||D4G2;|conn@1|a|I
+EinB[15:20]||D4G2;|conn@6|a|I
+Einn[1:18]||D4G2;|conn@0|a|I
+Eoutt[16:37]||D6G2;|conn@3|y|O
+X