migrate jelib->delib

[fleet.git] / chips / marina / electric / registersM.delib / shadowMux4.sch

diff --git a/chips/marina/electric/registersM.delib/shadowMux4.sch b/chips/marina/electric/registersM.delib/shadowMux4.sch
new file mode 100644 (file)
index 0000000..88e7236
--- /dev/null
+++ b/chips/marina/electric/registersM.delib/shadowMux4.sch
@@ -0,0 +1,59 @@
+HregistersM|8.10k
+
+# External Libraries:
+
+Lgates2inM|gates2inM
+
+LorangeTSMC090nm|orangeTSMC090nm
+
+LredFive|redFive
+
+# Cell shadowMux4;1{sch}
+CshadowMux4;1{sch}||schematic|1216073680001|1238334870912|I
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NOff-Page|conn@0||-23|0.5||||
+NOff-Page|conn@2||6|-11|||R|
+NOff-Page|conn@3||21|-1.5||||
+NOff-Page|conn@4||12|7|||RRR|
+IshadowMux4;1{ic}|dataMux4@0||23.5|11|||D5G4;
+IredFive:inv;1{ic}|i[1:4]|D5G3;Y6;|-12|0.5|||D0G4;|ATTR_Delay(D5G1;NPX2;Y-2;)I100|ATTR_X(D5G1.5;NPX1.5;Y2;)S10|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1
+Igates2inM:mux5;1{ic}|m[1:4]|D5G3;X2;Y-5;|12|-1.5|||D5G4;
+Ngeneric:Invisible-Pin|pin@2||0|25|||||ART_message(D5G6;)SshadowMux4
+Ngeneric:Invisible-Pin|pin@3||0|16|||||ART_message(D5G3;)Sies 30 January 2009
+Ngeneric:Invisible-Pin|pin@4||0|20|||||ART_message(D5G3;)Sfour non-storage shadow bits
+NWire_Pin|pin@7||6|-3.5||||
+NBus_Pin|pin@8||-0.5|0.5|-1|-1||
+NBus_Pin|pin@9||-0.5|3.5|-1|-1||
+NWire_Pin|pin@10||-42|-6||||
+NWire_Pin|pin@11||-42|-9.5||||
+NWire_Pin|pin@12||-30|-6||||
+NWire_Pin|pin@13||-30|-9.5||||
+NWire_Pin|pin@14||-18|-6||||
+NWire_Pin|pin@15||-18|-9.5||||
+NWire_Pin|pin@16||-6|-6||||
+NWire_Pin|pin@17||-6|-9.5||||
+IorangeTSMC090nm:wire90;1{ic}|wire90@0||-36|-6|||D0G4;|ATTR_L(D5G1;PUD)D251.8|ATTR_LEWIRE(P)I1|ATTR_layer(D5G1;NPY-1;)I1|ATTR_width(D5G1;NPY-2;)I3
+IorangeTSMC090nm:wire90;1{ic}|wire90@1||-24|-6|||D0G4;|ATTR_L(D5G1;PUD)D251.8|ATTR_LEWIRE(P)I1|ATTR_layer(D5G1;NPY-1;)I1|ATTR_width(D5G1;NPY-2;)I3
+IorangeTSMC090nm:wire90;1{ic}|wire90@2||-12|-6|||D0G4;|ATTR_L(D5G1;PUD)D251.8|ATTR_LEWIRE(P)I1|ATTR_layer(D5G1;NPY-1;)I1|ATTR_width(D5G1;NPY-2;)I3
+IorangeTSMC090nm:wire90;1{ic}|wire90@3||0|-6|||D0G4;|ATTR_L(D5G1;PUD)D251.8|ATTR_LEWIRE(P)I1|ATTR_layer(D5G1;NPY-1;)I1|ATTR_width(D5G1;NPY-2;)I3
+Awire|net@13|||1800|pin@7||6|-3.5|m[1:4]|inB[1]|11|-3.5
+Awire|net@16|||2700|conn@2|y|6|-9|pin@7||6|-3.5
+Abus|net@24||-0.5|IJ1800|conn@0|y|-21|0.5|i[1:4]|in|-14.5|0.5
+Abus|net@25||-0.5|IJ1800|pin@8||-0.5|0.5|m[1:4]|inA[1]|11|0.5
+Abus|net@27||-0.5|IJ1800|m[1:4]|out[1]|14|-1.5|conn@3|a|19|-1.5
+Abus|net@28||-0.5|IJ1800|i[1:4]|out|-9.5|0.5|pin@8||-0.5|0.5
+Awire|net@30|||0|wire90@0|a|-38.5|-6|pin@10||-42|-6
+Awire|net@32|||0|wire90@1|a|-26.5|-6|pin@12||-30|-6
+Awire|net@34|||0|wire90@2|a|-14.5|-6|pin@14||-18|-6
+Awire|net@36|||0|wire90@3|a|-2.5|-6|pin@16||-6|-6
+Abus|net@38||-0.5|IJ900|conn@4|y|12|5|m[1:4]|s[A][T,F]|12|1.5
+Abus|x[1:4]|D5G2;|-0.5|IJ2700|pin@8||-0.5|0.5|pin@9||-0.5|3.5
+Awire|x[1]|D5G2;||900|pin@10||-42|-6|pin@11||-42|-9.5
+Awire|x[2]|D5G2;||900|pin@12||-30|-6|pin@13||-30|-9.5
+Awire|x[3]|D5G2;||900|pin@14||-18|-6|pin@15||-18|-9.5
+Awire|x[4]|D5G2;||900|pin@16||-6|-6|pin@17||-6|-9.5
+Elit[16:19]|in[1:4]|D4G2;|conn@0|a|I
+Eout[16:19]|out[1:4]|D6G2;|conn@3|y|O
+Es[T,F]||D4G2;|conn@4|a|I
+Esign||D4G2;|conn@2|a|I
+X