migrate jelib->delib

[fleet.git] / chips / marina / electric / registersM.delib / signLogic.sch

diff --git a/chips/marina/electric/registersM.delib/signLogic.sch b/chips/marina/electric/registersM.delib/signLogic.sch
new file mode 100644 (file)
index 0000000..0d78027
--- /dev/null
+++ b/chips/marina/electric/registersM.delib/signLogic.sch
@@ -0,0 +1,62 @@
+HregistersM|8.10k
+
+# External Libraries:
+
+LorangeTSMC090nm|orangeTSMC090nm
+
+LredFive|redFive
+
+# Cell signLogic;1{sch}
+CsignLogic;1{sch}||schematic|1233362744221|1238334870912|I
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NOff-Page|conn@1||38.5|0||||
+NOff-Page|conn@2||-32.5|1||||
+NOff-Page|conn@3||34|22||||
+IredFive:inv;1{ic}|inv@0||26.5|0|||D0G4;|ATTR_Delay(D5G1;NPX2;Y-2;)I100|ATTR_X(D5G1.5;NPX1.5;Y2;)S80|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1
+IredFive:inv;1{ic}|inv@2||-20.5|1|||D0G4;|ATTR_Delay(D5G1;NPX2;Y-2;)I100|ATTR_X(D5G1.5;NPX1.5;Y2;)S30|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1
+IredFive:inv;1{ic}|inv@3||4.5|24|||D0G4;|ATTR_Delay(D5G1;NPX2;Y-2;)I100|ATTR_X(D5G1.5;NPX1.5;Y2;)S100|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1
+IredFive:inv;1{ic}|inv@4||18|24|||D0G4;|ATTR_Delay(D5G1;NPX2;Y-2;)I100|ATTR_X(D5G1.5;NPX1.5;Y2;)S80|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1
+IredFive:inv;1{ic}|inv@5||13.5|0|||D0G4;|ATTR_Delay(D5G1;NPX2;Y-2;)I100|ATTR_X(D5G1.5;NPX1.5;Y2;)S30|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1
+IredFive:nand2_sy;1{ic}|nand2_sy@0||-0.5|0|Y||D0G4;|ATTR_Delay(D5G1;NPX2.5;Y-3;)I100|ATTR_X(D5G1.5;NPX2.5;Y2.5;)S20|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1
+Ngeneric:Invisible-Pin|pin@0||-3|49|||||ART_message(D5G6;)SsignLogic
+Ngeneric:Invisible-Pin|pin@1||-3|35|||||ART_message(D5G3;)Sies 30 January 2009
+Ngeneric:Invisible-Pin|pin@2||-2.5|42|||||ART_message(D5G3;)S"these are the drivers for \"sign\" and \"s[T,F]\""
+NWire_Pin|pin@6||-6|-1||||
+NWire_Pin|pin@10||12|24||||
+NWire_Pin|pin@11||12|19.5||||
+NWire_Pin|pin@12||24|24||||
+NWire_Pin|pin@13||24|19.5||||
+NWire_Pin|pin@14||-6|1||||
+NWire_Pin|pin@15||-6|24||||
+NWire_Pin|pin@18||-6|-9||||
+Ngeneric:Invisible-Pin|pin@19||5|-6|||||ART_message(D3G2;)Ssign HI extends 1's.
+Ngeneric:Invisible-Pin|pin@20||6.5|16|||||ART_message(D3G2;)Ss[T] HI selects the LONG literal
+NWire_Pin|pin@23||-27|1||||
+NWire_Pin|pin@24||-27|6.5||||
+IsignLogic;1{ic}|signLogi@2||31|32|||D5G4;
+IorangeTSMC090nm:wire90;1{ic}|wire90@2||20|0|||D0G4;|ATTR_L(D5G1;PUD)D817.8999999999996|ATTR_LEWIRE(P)I1|ATTR_layer(D5G1;NPY-1;)I1|ATTR_width(D5G1;NPY-2;)I3
+IorangeTSMC090nm:wire90;1{ic}|wire90@4||-12|1|||D0G4;|ATTR_L(D5G1;PUD)D1334.3000000000002|ATTR_LEWIRE(P)I1|ATTR_layer(D5G1;NPY-1;)I1|ATTR_width(D5G1;NPY-2;)I3
+IorangeTSMC090nm:wire90;1{ic}|wire90@5||7|0|||D0G4;|ATTR_L(D5G1;PUD)D540.0|ATTR_LEWIRE(P)I1|ATTR_layer(D5G1;NPY-1;)I1|ATTR_width(D5G1;NPY-2;)I3
+Awire|inB[15]|D5G2;||900|pin@6||-6|-1|pin@18||-6|-9
+Awire|inB[20]|D5G2;||2700|pin@23||-27|1|pin@24||-27|6.5
+Awire|net@2|||1800|pin@10||12|24|inv@4|in|15.5|24
+Awire|net@7|||0|nand2_sy@0|ina|-3|1|pin@14||-6|1
+Awire|net@8|||0|pin@14||-6|1|wire90@4|b|-9.5|1
+Awire|net@9|||2700|pin@14||-6|1|pin@15||-6|24
+Awire|net@10|||1800|pin@15||-6|24|inv@3|in|2|24
+Awire|net@12|||0|inv@0|in|24|0|wire90@2|b|22.5|0
+Awire|net@13|||0|wire90@2|a|17.5|0|inv@5|out|16|0
+Awire|net@14|||0|inv@5|in|11|0|wire90@5|b|9.5|0
+Awire|net@19|||1800|inv@2|out|-18|1|wire90@4|a|-14.5|1
+Awire|net@21|||0|wire90@5|a|4.5|0|nand2_sy@0|out|2|0
+Awire|net@22|||1800|pin@6||-6|-1|nand2_sy@0|inb|-3|-1
+Awire|net@28|||1800|inv@0|out|29|0|conn@1|a|36.5|0
+Awire|net@29|||1800|inv@3|out|7|24|pin@10||12|24
+Awire|net@30|||1800|inv@4|out|20.5|24|pin@12||24|24
+Awire|net@34|||0|inv@2|in|-23|1|pin@23||-27|1
+Awire|s[F]|D5G2;||900|pin@12||24|24|pin@13||24|19.5
+Awire|s[T]|D5G2;||900|pin@10||12|24|pin@11||12|19.5
+EinB[15,20]||D4G2;|conn@2|a|I
+Es[T,F]||D6G2;|conn@3|y|O
+Esign||D6G2;|conn@1|y|O
+X