migrate jelib->delib

[fleet.git] / chips / marina / electric / stageGroupsM.delib / properStopper.sch

diff --git a/chips/marina/electric/stageGroupsM.delib/properStopper.sch b/chips/marina/electric/stageGroupsM.delib/properStopper.sch
new file mode 100644 (file)
index 0000000..919720a
--- /dev/null
+++ b/chips/marina/electric/stageGroupsM.delib/properStopper.sch
@@ -0,0 +1,61 @@
+HstageGroupsM|8.10k
+
+# External Libraries:
+
+LorangeTSMC090nm|orangeTSMC090nm
+
+LstagesM|stagesM
+
+# Cell properStopper;1{sch}
+CproperStopper;1{sch}||schematic|1182121322015|1243246708862|I
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NOff-Page|conn@1||-21|-7|||Y|
+NOff-Page|conn@2||22|-7||||
+NOff-Page|conn@4||-21|9|||Y|
+NOff-Page|conn@5||-21|2|||Y|
+NOff-Page|conn@6||-21|6|||Y|
+NOff-Page|conn@7||22|6||||
+NOff-Page|conn@8||22|2||||
+NOff-Page|conn@9||22|9||||
+NOff-Page|conn@10||22|12||||
+NOff-Page|conn@11||-21|12|||Y|
+NOff-Page|conn@14||-3|-2.5||||
+NOff-Page|conn@15||-12|-13|||RRR|
+IstagesM:drainStage;1{ic}|drainSta@1||12|0|||D5G4;
+IstagesM:fillStage;1{ic}|fillStag@1||-12|0|||D5G4;
+Ngeneric:Invisible-Pin|pin@3||-12|41|||||ART_message(D5FLeave alone;G5;)SproperStopper
+Ngeneric:Invisible-Pin|pin@4||-10.5|33|||X||ART_message(D5FLeave alone;G3;)Sies 21 February 2009
+Ngeneric:Invisible-Pin|pin@5||-10|29|||||ART_message(D5FLeave alone;G2;)SA complete pair to load and unload
+Ngeneric:Invisible-Pin|pin@6||-22.5|24.5|||||ART_message(D3G2;)S[layout for control in center,and m2 ports,ies 21 February 2009]
+IproperStopper;1{ic}|properSt@0||23.5|29|||D5G4;
+IorangeTSMC090nm:wire90;1{ic}|wire90@0||1|2|||D0G4;|ATTR_L(D5G1;PUD)D2080.3999999999996|ATTR_LEWIRE(P)I1|ATTR_layer(D5G1;NPY-1;)I1|ATTR_width(D5G1;NPY-2;)I3
+Abus|net@2||-0.5|IJ1800|fillStag@1|sor[1:9]|-10|6|drainSta@1|sir[1:9]|11|6
+Abus|net@3||-0.5|IJ1800|fillStag@1|soc[1:9]|-10|9|drainSta@1|sic[1:9]|11|9
+Abus|net@4||-0.5|IJ1800|conn@1|y|-19|-7|fillStag@1|in[1:37],ain[T,1:14]|-14|-7
+Abus|net@6||-0.5|IJ1800|drainSta@1|out[1:37],aout[T,1:14]|14|-7|conn@2|a|20|-7
+Abus|net@10||-0.5|IJ0|fillStag@1|sir[1:9]|-13|6|conn@6|y|-19|6
+Abus|net@15||-0.5|IJ1800|drainSta@1|sor[1:9]|14|6|conn@7|a|20|6
+Abus|net@16||-0.5|IJ1800|drainSta@1|soc[1:9]|14|9|conn@9|a|20|9
+Abus|net@18||-0.5|IJ0|fillStag@1|sic[1:9]|-13|9|conn@4|y|-19|9
+Awire|net@19|||0|fillStag@1|pred|-14|2|conn@5|y|-19|2
+Awire|net@20|||1800|drainSta@1|succ|14|2|conn@8|a|20|2
+Abus|net@21||-0.5|IJ1800|conn@11|y|-19|12|fillStag@1|sid[1:9]|-13|12
+Abus|net@22||-0.5|IJ1800|fillStag@1|sod[1:9]|-10|12|conn@10|a|20|12
+Awire|net@41|||1800|fillStag@1|succ|-10|2|wire90@0|a|-1.5|2
+Awire|net@42|||1800|wire90@0|b|3.5|2|drainSta@1|pred|10|2
+Abus|net@65||-0.5|IJ1800|fillStag@1|out[1:37],aout[T,1:14]|-10|-7|drainSta@1|in[1:37],ain[T,1:14]|10|-7
+Awire|net@66|||0|conn@14|a|-5|-2.5|fillStag@1|fire_1|-9|-2.5
+Awire|net@69|||2700|conn@15|a|-12|-11|fillStag@1|succ_1|-12|-9
+Ein[1:37],ain[T,1:14]|ain[TT,1:14],in[1:37]|D4G3;|conn@1|a|I
+Eout[1:37],aout[T,1:14]|aout[TT,1:14],out[1:37]|D6G3;|conn@2|y|O
+Eextra||D6G2;|conn@14|y|O
+Efire||D6G2;|conn@15|y|O
+Epred||D4G3;|conn@5|a|I
+Esic[1:9]||D4G3;|conn@4|a|B
+Esid[1:9]||D4G3;|conn@11|a|B
+Esir[1:9]||D4G3;|conn@6|a|B
+Esoc[1:9]||D6G3;|conn@9|y|B
+Esod[1:9]||D6G3;|conn@10|y|B
+Esor[1:9]||D6G3;|conn@7|y|B
+Esucc||D6G3;|conn@8|y|O
+X