migrate jelib->delib

[fleet.git] / chips / marina / electric / stagesM.delib / altEndDockStage.sch

diff --git a/chips/marina/electric/stagesM.delib/altEndDockStage.sch b/chips/marina/electric/stagesM.delib/altEndDockStage.sch
new file mode 100644 (file)
index 0000000..a9f7f5a
--- /dev/null
+++ b/chips/marina/electric/stagesM.delib/altEndDockStage.sch
@@ -0,0 +1,118 @@
+HstagesM|8.10k
+
+# External Libraries:
+
+LdriversM|driversM
+
+LgaspM|gaspM
+
+LorangeTSMC090nm|orangeTSMC090nm
+
+LregistersM|registersM
+
+LscanM|scanM
+
+LwiresL|wiresL
+
+# Cell altEndDockStage;2{sch}
+CaltEndDockStage;2{sch}||schematic|1227457806942|1243246708862|I
+IaltEndDockStage;1{ic}|altEndSt@0||-28|15|||D5G4;
+IgaspM:anAltEnd;1{ic}|anAltEnd@1||0|0|||D5G4;
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NOff-Page|conn@0||-8.5|2|||Y|
+NOff-Page|conn@1||8|0|||Y|
+NOff-Page|conn@2||-8.5|-2|||Y|
+NOff-Page|conn@6||12.5|-43.5||||
+NOff-Page|conn@7||-11|-41||||
+NOff-Page|conn@8||-11.5|-46.5||||
+NOff-Page|conn@9||33.5|-21|||YRRR|
+NOff-Page|conn@10||33.5|6|||R|
+IregistersM:ins2in20Ax36;1{ic}|ins2in20@0||0|-43.5|Y||D5G4;
+IdriversM:latchDriver60;1{ic}|latchDri@2||-15|-18|RRR||D5G4;
+IdriversM:latchDriver60;1{ic}|latchDri@3||15|-18|YR||D5G4;
+NWire_Pin|pin@0||15|-27||||
+NWire_Pin|pin@1||-15|-27|||RR|
+NWire_Pin|pin@2||6|-6|||X|
+NWire_Pin|pin@3||-6|-6|||XRR|
+NBus_Pin|pin@4||0|-9|-1|-1||
+NWire_Pin|pin@5||-6|-12|||X|
+NWire_Pin|pin@6||6|-12|||X|
+NWire_Pin|pin@7||-15|-12||||
+NWire_Pin|pin@8||15|-12||||
+Ngeneric:Invisible-Pin|pin@9||0|34|||||ART_message(D5G4;)S[end an alternating end,without scan chain]
+Ngeneric:Invisible-Pin|pin@10||-1.5|42.5|||||ART_message(D5G6;)SaltEndDockStage
+NWire_Pin|pin@21||5.5|-27||||
+NWire_Pin|pin@23||-4.5|-27||||
+NWire_Pin|pin@26||5.5|-32||||
+NWire_Pin|pin@30||-4.5|-31.5||||
+NBus_Pin|pin@51||-6|-46.5|-1|-1||
+NBus_Pin|pin@52||-6|-44.5|-1|-1||
+NBus_Pin|pin@53||-6|-41|-1|-1||
+NBus_Pin|pin@54||-6|-42.5|-1|-1||
+NWire_Pin|pin@55||23.5|-14||||
+NWire_Pin|pin@56||23.5|-11.5||||
+NWire_Pin|pin@57||24|-8||||
+NWire_Pin|pin@58||24|-5.5||||
+NWire_Pin|pin@60||24|0.5||||
+NWire_Pin|pin@61||24|-2.5||||
+NBus_Pin|pin@63||1|8.5|-1|-1||
+NWire_Pin|pin@64||-1|13||||
+NWire_Pin|pin@65||43.5|-12||||
+NWire_Pin|pin@66||43.5|-16||||
+NBus_Pin|pin@67||-2|-34|-1|-1|Y|
+Ngeneric:Invisible-Pin|pin@68||-3|25.5|||||ART_message(D5FLeave alone;G3;)Sies 3 April 2009
+IscanM:scanEx3;1{ic}|scanEx3@0||33.5|-6|||D5G4;
+IwiresL:tranCap;1{ic}|tc[1:21]|D5G1;X2;Y2;|18|15|||D5G4;
+IorangeTSMC090nm:wire90;1{ic}|wire90@0||10.5|-12|RR||D0G4;|ATTR_L(D5FLeave alone;G1;PUD)D1336.1999999999998|ATTR_LEWIRE(P)I1|ATTR_layer(D5FLeave alone;G1;NPY-1;)I1|ATTR_width(D5FLeave alone;G1;NPY-2;)I3
+IorangeTSMC090nm:wire90;1{ic}|wire90@1||-10.5|-12|||D0G4;|ATTR_L(D5FLeave alone;G1;PUD)D1307.0|ATTR_LEWIRE(P)I1|ATTR_layer(D5FLeave alone;G1;NPY-1;)I1|ATTR_width(D5FLeave alone;G1;NPY-2;)I3
+IorangeTSMC090nm:wire90;1{ic}|wire90@2||10.5|-27|RR||D0G4;|ATTR_L(D5FLeave alone;G1;PUD)D1336.1999999999998|ATTR_LEWIRE(P)I1|ATTR_layer(D5FLeave alone;G1;NPY-1;)I1|ATTR_width(D5FLeave alone;G1;NPY-2;)I3
+IorangeTSMC090nm:wire90;1{ic}|wire90@3||-10.5|-27|||D0G4;|ATTR_L(D5FLeave alone;G1;PUD)D1307.0|ATTR_LEWIRE(P)I1|ATTR_layer(D5FLeave alone;G1;NPY-1;)I1|ATTR_width(D5FLeave alone;G1;NPY-2;)I3
+Abus|fire[A,B]|D5G2;|-0.5|I2700|pin@4||0|-9|anAltEnd@1|fire[A,B]|0|-4
+Awire|fire[A]|D5G2;||2700|pin@5||-6|-12|pin@3||-6|-6
+Awire|fire[B]|D5G2;||2700|pin@6||6|-12|pin@2||6|-6
+Awire|mc|D5G2;||900|pin@65||43.5|-12|pin@66||43.5|-16
+Awire|mc|D5G2;||900|pin@64||-1|13|anAltEnd@1|mc|-1|4
+Awire|net@0|||0|anAltEnd@1|predB|-3|-2|conn@2|y|-6.5|-2
+Awire|net@1|||0|anAltEnd@1|predA|-3|2|conn@0|y|-6.5|2
+Awire|net@2|||0|conn@1|a|6|0|anAltEnd@1|succ|3|0
+Awire|net@3|||0|wire90@1|a|-13|-12|pin@7||-15|-12
+Awire|net@4|||900|pin@7||-15|-12|latchDri@2|in|-15|-14
+Awire|net@5|||1800|wire90@1|b|-8|-12|pin@5||-6|-12
+Awire|net@6|||1800|pin@6||6|-12|wire90@0|b|8|-12
+Awire|net@7|||1800|wire90@0|a|13|-12|pin@8||15|-12
+Awire|net@8|||900|pin@8||15|-12|latchDri@3|in|15|-14
+Awire|net@23|||1800|wire90@2|a|13|-27|pin@0||15|-27
+Awire|net@25|||0|wire90@2|b|8|-27|pin@21||5.5|-27
+Awire|net@27|||1800|pin@1||-15|-27|wire90@3|a|-13|-27
+Awire|net@28|||1800|wire90@3|b|-8|-27|pin@23||-4.5|-27
+Awire|net@41|||900|latchDri@3|out|15|-22|pin@0||15|-27
+Awire|net@42|||900|latchDri@2|out|-15|-22|pin@1||-15|-27
+Abus|net@59||-0.5|IJ1800|conn@8|y|-9.5|-46.5|pin@51||-6|-46.5
+Abus|net@60||-0.5|IJ2700|pin@51||-6|-46.5|pin@52||-6|-44.5
+Abus|net@62||-0.5|IJ1800|conn@7|y|-9|-41|pin@53||-6|-41
+Abus|net@63||-0.5|IJ900|pin@53||-6|-41|pin@54||-6|-42.5
+Awire|net@66|||0|scanEx3@0|dIn[1]|28.5|-14|pin@55||23.5|-14
+Awire|net@69|||1800|pin@61||24|-2.5|scanEx3@0|dIn[3]|28.5|-2.5
+Awire|net@70|||1800|pin@57||24|-8|scanEx3@0|dIn[2]|28.5|-8
+Abus|net@74||-0.5|IJ900|conn@10|a|33.5|4|scanEx3@0|sor[1:9]|33.5|1.5
+Abus|net@77||-0.5|IJ2700|conn@9|y|33.5|-19|scanEx3@0|sir[1:9]|33.5|-14
+Awire|net@79|||1800|scanEx3@0|mc|38.5|-12|pin@65||43.5|-12
+Abus|net@83||-0.5|IJ0|ins2in20@0|inA[1:36]|-3|-42.5|pin@54||-6|-42.5
+Abus|net@84||-0.5|IJ1800|pin@52||-6|-44.5|ins2in20@0|inB[1:36]|-3|-44.5
+Abus|net@86||-0.5|IJ1800|ins2in20@0|out[1:36]|3|-43.5|conn@6|a|10.5|-43.5
+Abus|s[1:3]|D5G2;|-0.5|IJ2700|anAltEnd@1|s[1:3]|1|4|pin@63||1|8.5
+Awire|s[1]|D5G2;||2700|pin@55||23.5|-14|pin@56||23.5|-11.5
+Awire|s[2]|D5G2;||2700|pin@57||24|-8|pin@58||24|-5.5
+Awire|s[3]|D5G2;||2700|pin@61||24|-2.5|pin@60||24|0.5
+Abus|take[A,B]|D5G2;|-0.5|IJ2700|ins2in20@0|hcl[B][1]|-2|-40.5|pin@67||-2|-34
+Awire|take[A]|D5G2;||900|pin@23||-4.5|-27|pin@30||-4.5|-31.5
+Awire|take[B]|D5G2;||900|pin@21||5.5|-27|pin@26||5.5|-32
+EinA[1:36]||D4G2;|conn@7|a|I
+EinB[1:36]||D4G2;|conn@8|a|I
+Eout[1:36]||D6G2;|conn@6|y|O
+EpredA||D4G2;|conn@0|a|I
+EpredB||D4G2;|conn@2|a|I
+Esir[1:9]||D4G2;|conn@9|a|I
+Esor[1:9]||D6G2;|conn@10|y|O
+Esucc||D6G2;|conn@1|y|O
+X