migrate jelib->delib

[fleet.git] / chips / marina / electric / stagesM.delib / mOneDockStage.sch

diff --git a/chips/marina/electric/stagesM.delib/mOneDockStage.sch b/chips/marina/electric/stagesM.delib/mOneDockStage.sch
new file mode 100644 (file)
index 0000000..cf9a4a6
--- /dev/null
+++ b/chips/marina/electric/stagesM.delib/mOneDockStage.sch
@@ -0,0 +1,75 @@
+HstagesM|8.10k
+
+# External Libraries:
+
+LdriversM|driversM
+
+LoneHotM|oneHotM
+
+LorangeTSMC090nm|orangeTSMC090nm
+
+LregistersM|registersM
+
+LscanM|scanM
+
+LwiresL|wiresL
+
+# Cell mOneDockStage;1{sch}
+CmOneDockStage;1{sch}||schematic|1227450428956|1243246708862|I
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NOff-Page|conn@0||-12|3|||Y|
+NOff-Page|conn@3||18.5|-24||||
+NOff-Page|conn@4||0|-30||||
+NOff-Page|conn@5||29|-30||||
+NOff-Page|conn@6||12|3||||
+NOff-Page|conn@7||-9|16|||Y|
+NOff-Page|conn@8||12|16||||
+NOff-Page|conn@9||13|-2||||
+IregistersM:ins1in20Bx36;1{ic}|ins1in20@0||14|-30|Y||D5G4;
+IdriversM:latchDriver60;1{ic}|latchDri@1||12|-17|RRR||D5G4;
+ImOneDockStage;1{ic}|mOneDocK@0||34.5|20.5|||D5G4;
+IoneHotM:minusOne;1{ic}|minusOne@0||0|0|||D5G4;
+Ngeneric:Invisible-Pin|pin@0||2.5|34|||||ART_message(D5G4;)Sthe M1 stage with scan chain
+Ngeneric:Invisible-Pin|pin@1||1|39.5|||||ART_message(D5G6;)SmOneDockStage
+NWire_Pin|pin@3||12|-9||||
+NWire_Pin|pin@4||12|-24||||
+NWire_Pin|pin@7||0|-9||||
+NWire_Pin|pin@17||-2|21||||
+NBus_Pin|pin@22||-9|-2|-1|-1||
+NBus_Pin|pin@23||-9|-7|-1|-1||
+NWire_Pin|pin@24||-18|0||||
+NWire_Pin|pin@25||-18|-4||||
+Ngeneric:Invisible-Pin|pin@26||-0.5|26|||||ART_message(D5FLeave alone;G3;)Sies 3 April 2009
+IscanM:scanEx1;1{ic}|scanEx1@0||4|16|YRRR||D5G4;
+IwiresL:tranCap;1{ic}|tc[1:19]|D5G3;X2;Y2;|-24|16|||D5G4;
+IorangeTSMC090nm:wire90;1{ic}|wire90@1||6|-9|||D0G4;|ATTR_L(D5FLeave alone;G1;PUD)D793.6|ATTR_LEWIRE(P)I1|ATTR_layer(D5FLeave alone;G1;NPY-1;)I1|ATTR_width(D5FLeave alone;G1;NPY-2;)I3
+Awire|fire[1]|D5G2;||2700|latchDri@1|in|12|-13|pin@3||12|-9
+Awire|net@3|||1800|pin@4||12|-24|conn@3|a|16.5|-24
+Awire|net@4|||900|latchDri@1|out|12|-21|pin@4||12|-24
+Abus|net@5||-0.5|IJ0|ins1in20@0|in[1:36]|11|-30|conn@4|y|2|-30
+Abus|net@6||-0.5|IJ1800|ins1in20@0|out[1:36]|17|-30|conn@5|a|27|-30
+Awire|net@11|||0|wire90@1|a|3.5|-9|pin@7||0|-9
+Awire|net@12|||0|pin@3||12|-9|wire90@1|b|8.5|-9
+Abus|net@30||-0.5|IJ1800|conn@7|y|-7|16|scanEx1@0|sir[1:9]|2|16
+Abus|net@31||-0.5|IJ1800|scanEx1@0|sor[1:9]|6|16|conn@8|a|10|16
+Awire|net@35|||0|scanEx1@0|mc|3|21|pin@17||-2|21
+Awire|net@40|||2700|ins1in20@0|hcl[1]|12|-27|pin@4||12|-24
+Awire|net@47|||900|scanEx1@0|dIn[1]|2|11|minusOne@0|succ_1|2|6
+Awire|net@48|||2700|minusOne@0|pred_1|-2|5|pin@17||-2|21
+Awire|net@49|||900|minusOne@0|take[P]|0|-5|pin@7||0|-9
+Awire|net@50|||0|minusOne@0|pred|-4|3|conn@0|y|-10|3
+Awire|net@51|||1800|minusOne@0|succ|4|3|conn@6|a|10|3
+Abus|net@52||-0.5|IJ0|minusOne@0|pred_1@931992807|-4|-2|pin@22||-9|-2
+Abus|net@54||-0.5|IJ1800|minusOne@0|out[1:6][T,F]|4|-2|conn@9|a|11|-2
+Awire|net@55|||0|minusOne@0|pred_1@740900629|-4|0|pin@24||-18|0
+Awire|ring[30]|D5G2;||900|pin@24||-18|0|pin@25||-18|-4
+Abus|ring[31:36]|D5G2;|-0.5|IJ900|pin@22||-9|-2|pin@23||-9|-7
+Eout[1:36]|m1[1:36]|D6G2;|conn@5|y|O
+Esucc_1|m1cate[1:6][T,F]|D6G2;|conn@9|y|O
+Epred|pred[R]|D4G2;|conn@0|a|I
+Ein[1:36]|ring[1:36]|D4G2;|conn@4|a|I
+Esir[1:9]||D4G2;|conn@7|a|I
+Esor[1:9]||D6G2;|conn@8|y|O
+Esucc|succ[m1]|D6G2;|conn@6|y|O
+Etake[1]|take[m1]|D6G2;|conn@3|y|O
+X