migrate jelib->delib

[fleet.git] / chips / marina / electric / stagesM.delib / plainDockStage.sch

diff --git a/chips/marina/electric/stagesM.delib/plainDockStage.sch b/chips/marina/electric/stagesM.delib/plainDockStage.sch
new file mode 100644 (file)
index 0000000..8340cb5
--- /dev/null
+++ b/chips/marina/electric/stagesM.delib/plainDockStage.sch
@@ -0,0 +1,68 @@
+HstagesM|8.10k
+
+# External Libraries:
+
+LdriversM|driversM
+
+LgaspM|gaspM
+
+LorangeTSMC090nm|orangeTSMC090nm
+
+LregistersM|registersM
+
+LscanM|scanM
+
+LwiresL|wiresL
+
+# Cell plainDockStage;1{sch}
+CplainDockStage;1{sch}||schematic|1227450428956|1243246708862|I
+IgaspM:aStage;1{ic}|aStage@1||0|0|||D5G4;
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NOff-Page|conn@0||-12|0|||Y|
+NOff-Page|conn@3||18.5|-24||||
+NOff-Page|conn@4||0|-30||||
+NOff-Page|conn@5||29|-30||||
+NOff-Page|conn@6||12|0||||
+NOff-Page|conn@7||-9|16|||Y|
+NOff-Page|conn@8||9|16||||
+IregistersM:ins1in20Bx36;1{ic}|ins1in20@0||14|-30|Y||D5G4;
+IdriversM:latchDriver60;1{ic}|latchDri@1||12|-15|RRR||D5G4;
+Ngeneric:Invisible-Pin|pin@0||2.5|34|||||ART_message(D5G4;)Sone stage with scan chain
+Ngeneric:Invisible-Pin|pin@1||1|39.5|||||ART_message(D5G6;)SplainDockStage
+NWire_Pin|pin@3||12|-6||||
+NWire_Pin|pin@4||12|-24||||
+NWire_Pin|pin@7||0|-6||||
+NWire_Pin|pin@17||-4|21||||
+NWire_Pin|pin@18||-4|8||||
+NWire_Pin|pin@19||-1|8||||
+Ngeneric:Invisible-Pin|pin@20||-0.5|26|||||ART_message(D5FLeave alone;G3;)Sies 3 April 2009
+IscanM:scanEx1;1{ic}|scanEx1@0||3|16|YRRR||D5G4;
+IplainDockStage;1{ic}|shortSte@0||-31|17|||D5G4;
+IwiresL:tranCap;1{ic}|tc[1:3]|D5G1;X2;Y1;|26.5|8|||D5G4;
+IorangeTSMC090nm:wire90;1{ic}|wire90@1||6|-6|||D0G4;|ATTR_L(D5FLeave alone;G1;PUD)D791.7000000000004|ATTR_LEWIRE(P)I1|ATTR_layer(D5FLeave alone;G1;NPY-1;)I1|ATTR_width(D5FLeave alone;G1;NPY-2;)I3
+Awire|fire[1]|D5G2;||2700|latchDri@1|in|12|-11|pin@3||12|-6
+Awire|net@0|||1800|conn@0|y|-10|0|aStage@1|pred|-3|0
+Awire|net@1|||2700|pin@7||0|-6|aStage@1|fire|0|-4
+Awire|net@3|||1800|pin@4||12|-24|conn@3|a|16.5|-24
+Awire|net@4|||900|latchDri@1|out|12|-19|pin@4||12|-24
+Abus|net@5||-0.5|IJ0|ins1in20@0|in[1:36]|11|-30|conn@4|y|2|-30
+Abus|net@6||-0.5|IJ1800|ins1in20@0|out[1:36]|17|-30|conn@5|a|27|-30
+Awire|net@7|||0|conn@6|a|10|0|aStage@1|succ|3|0
+Awire|net@11|||0|wire90@1|a|3.5|-6|pin@7||0|-6
+Awire|net@12|||0|pin@3||12|-6|wire90@1|b|8.5|-6
+Abus|net@30||-0.5|IJ1800|conn@7|y|-7|16|scanEx1@0|sir[1:9]|1|16
+Abus|net@31||-0.5|IJ1800|scanEx1@0|sor[1:9]|5|16|conn@8|a|7|16
+Awire|net@35|||0|scanEx1@0|mc|2|21|pin@17||-4|21
+Awire|net@36|||900|pin@17||-4|21|pin@18||-4|8
+Awire|net@37|||1800|pin@18||-4|8|pin@19||-1|8
+Awire|net@38|||900|pin@19||-1|8|aStage@1|mc|-1|4
+Awire|net@40|||2700|ins1in20@0|hcl[1]|12|-27|pin@4||12|-24
+Awire|net@41|||900|scanEx1@0|dIn[1]|1|11|aStage@1|s[1]|1|4
+Ein[1:36]||D4G2;|conn@4|a|I
+Eout[1:36]||D6G2;|conn@5|y|O
+Epred||D4G2;|conn@0|a|I
+Esir[1:9]||D4G2;|conn@7|a|I
+Esor[1:9]||D6G2;|conn@8|y|O
+Esucc||D6G2;|conn@6|y|O
+Etake[1]||D6G2;|conn@3|y|O
+X