migrate jelib->delib

[fleet.git] / chips / marina / electric / wiresL.delib / bitAssignments.sch

diff --git a/chips/marina/electric/wiresL.delib/bitAssignments.sch b/chips/marina/electric/wiresL.delib/bitAssignments.sch
new file mode 100644 (file)
index 0000000..01380b6
--- /dev/null
+++ b/chips/marina/electric/wiresL.delib/bitAssignments.sch
@@ -0,0 +1,8 @@
+HwiresL|8.10k
+
+# Cell bitAssignments;1{sch}
+CbitAssignments;1{sch}||schematic|1225032312390|1240677374881|
+Ngeneric:Facet-Center|art@0||0|0||||AV
+IbitAssignments;1{ic}|bitAssig@0||3|8||V|D5G4;
+Ngeneric:Invisible-Pin|pin@0||-4.5|6|||||ART_message(D3G1.5;)S[updated 25 April 09,To = bit 15 HI is make Token output,Do = bit 16 HI is make Data output,Dc = bit 17 HI is capture data,Di = bit 18 HI is wait for data input,Ti = bit 19 HI is wait for token input,LL = bit 20 LO is immediate to a counter,LL = bit 20 HI is D to a counter OR,LL = bit 20 HI is long literal,"rD = bit 21 HI removes flag[D]",Fl = bit 22 HI loads flags,Ld = bit 23 HI loads OLC or ILC,. . . . bit 21 decides which HI = OLC,. . . . bit 20 decides where from,Co = bit 24 HI decrements OLC,Mv = bit 25 HI executes move,Tp = bit 26 HI allows torpedo,Lt = bit 27 HI does literal,bit 28 HI marks a TAIL,bit 29 HI is an ABORT,bit 30 HI marks a HEAD]
+X