migrate jelib->delib

[fleet.git] / chips / marina / electric / wiresL.delib / centerPins.lay

diff --git a/chips/marina/electric/wiresL.delib/centerPins.lay b/chips/marina/electric/wiresL.delib/centerPins.lay
new file mode 100644 (file)
index 0000000..1a4d678
--- /dev/null
+++ b/chips/marina/electric/wiresL.delib/centerPins.lay
@@ -0,0 +1,30 @@
+HwiresL|8.10k
+
+# Cell centerPins;1{lay}
+CcenterPins;1{lay}||cmos90|1180462114023|1238257435226|I|DRC_last_good_drc_bit()I10|DRC_last_good_drc_date()G1242129162262|FACET_characteristic_spacing()D[0.0,144.0]
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NMetal-2-Pin|pin@3||0|3.9||||
+NMetal-2-Pin|pin@4||0|22||||
+NMetal-2-Pin|pin@5||0|11.7||||
+NMetal-2-Pin|pin@6||0|-22||||
+NMetal-2-Pin|pin@7||0|-11.7||||
+NMetal-2-Pin|pin@8||0|-3.9||||
+NMetal-2-Pin|pin@9||0|22||||
+NMetal-2-Pin|pin@10||0|11.7||||
+NMetal-2-Pin|pin@11||0|3.9||||
+NMetal-2-Pin|pin@12||0|-3.9||||
+NMetal-2-Pin|pin@13||0|-11.7||||
+NMetal-2-Pin|pin@14||0|-22||||
+Ametal-2|net@0||6.2|S1800|pin@4||0|22|pin@9||0|22
+Ametal-2|net@1||1.2|S1800|pin@5||0|11.7|pin@10||0|11.7
+Ametal-2|net@2||1.2|S1800|pin@3||0|3.9|pin@11||0|3.9
+Ametal-2|net@3||1.2|S1800|pin@8||0|-3.9|pin@12||0|-3.9
+Ametal-2|net@4||1.2|S1800|pin@7||0|-11.7|pin@13||0|-11.7
+Ametal-2|net@5||6.2|S1800|pin@6||0|-22|pin@14||0|-22
+Ehca[A]||D5G2;|pin@8||I
+Ehca[B]||D5G2;|pin@3||I
+Ehcd[A]||D5G2;|pin@7||I
+Ehcd[B]||D5G2;|pin@5||I
+Evdd||D5G2;|pin@4||P
+Evdd_1||D5G2;|pin@6||P
+X